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In theory, both are affected by process variation in very similar ways. However, LVT cells are usually utilized in your critical paths, where process variation really hurts performance and timing closure. I'd say you are more worried about the effects on LVT cells, not necessarily because LVT cells suffer more from variation.
Subthreshold leakage is going to be more variable in LVT
since you are closer to the limiting gate drive (=GND).
I have also seen (in SOI particularly) that lightly doped
channels are more susceptible to outside influences such
as charging of local other-than-gate oxides.
But what you will see, depends on the foundry and flow,
and "how low is low?".
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