kurax
Newbie level 4
I have a design like this,
.
.
and so on
Here A_main and A_copy are 32 bit in size.
Unfortunately the A_main, B_main, C_main, D_main, are placed far apart. This causes a long routing path to Z. Also the clock is 2GHz which cant be relaxed, so its hard to close timing.
What can I do to reduce setup timing violation? I am trying to add a F1_reg to pipeline it before oring. Will this work? Is there anything else I can do? The violations are around "-50" to "-100"ps.
Code:
always @ (posedge X) begin
if (Y) begin
A_main <= 'b0;
A_x <= 'b0;
end else begin
A_main <= A_d;
A_x <= ^d;
end
end
assign A_copy = A_main;
assign A_d = d;
assign F1 = A_x ^ (^A_copy);
assign F2 = B_x ^ (^B_copy);
.
.
and so on
Here A_main and A_copy are 32 bit in size.
Code:
Z = F1 | F2 | F3 | F4;
What can I do to reduce setup timing violation? I am trying to add a F1_reg to pipeline it before oring. Will this work? Is there anything else I can do? The violations are around "-50" to "-100"ps.