How to fix setup timing violations for a design with high speed clock?

kurax said:

Thanks. But is there a way to do it without retiming?

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ThisIsNotSam said:

Yes... write better code?

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kurax said:

I have a design like this,

Code:

always @ (posedge X) begin
if (Y) begin
A_main <= 'b0;
A_x <= 'b0;
end else begin
A_main <= A_d;
A_x <= ^d;
end
end

assign A_copy = A_main;
assign A_d = d;
assign F1 = A_x ^ (^A_copy);
assign F2 = B_x ^ (^B_copy);

.
.
and so on

Here A_main and A_copy are 32 bit in size.

Code:

Z = F1 | F2 | F3 | F4;

Unfortunately the A_main, B_main, C_main, D_main, are placed far apart. This causes a long routing path to Z. Also the clock is 2GHz which cant be relaxed, so its hard to close timing.

What can I do to reduce setup timing violation? I am trying to add a F1_reg to pipeline it before oring. Will this work? Is there anything else I can do? The violations are around "-50" to "-100"ps.

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swabhi812 said:

1. Can you use higher metal layers for routing to reduce interconnect delay?
2. Pipeline.
3. Upsize cells.
4. Add buffers to reduces interconnect delay.
5. Add low Vt cells which are faster but more power hungry.

As in you have lot of options. Just use all the basics of reducing delay.

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