FPGA ALM or LAB estimated size

Hi everyone,

I am doing a project and I need to show some estimated values.

I have to compare the size of a custom program in FPGA and in ASIC. Quartus II gives me the ALM number which my program needs and now I have to find the size of these ALMs. I have tried to find the size of one ALM or one LAB (10 ALMs + interconnection) but I didn't find nothing. I have tried to know how many transistors one ALM has. I have found some data about this as the last graphic of this paper: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=606687 but it does not make sense for me. I read that one cluster or CLB (Configration Logic Block) has 8 ALMs. Looking the graphic, arround 800 transistors per BLE (Basic Logic Element) (BLE = ALM in these case). One Stratix V has 300.000 ALMs more or less and it uses 28nm TSCM technology. So: 300.000x800x28nm=6.72 m...of course it cannot be possible .

Any idea? Summarizing I need to know how can I calculate a coheren estimated value of LAB or ALM size.

Thank you so much,
Pablo.

I have to compare the size of a custom program in FPGA and in ASIC.

Click to expand...

Do you mean to compare a logic implemented in an ASIC and the same implemented in a FPGA?

You may want to go through this once (although Xilinx FPGA)-
https://www.edaboard.com/showthread...th-Xilinx-FPGA-LUTs&highlight=gate+equivalent

I conclude that you didn't take a closer look to the FPGA hardware handbook describing the structure of the FPGA fabric, particularly logic elements.

Also your math needs improvement

One Stratix V has 300.000 ALMs more or less and it uses 28nm TSCM technology. So: 300.000x800x28nm=6.72 m...of course it cannot be possible

Click to expand...

Assuming a transistor size of 28x28 nm (it's actually a bit larger, 28 nm is the structure size) would result in a 0.5*0.5 mm square chip, multiply by 5 or 10 and get the right order of magnitude…

When translating to ASIC, you'll look to the actual LUT usage statistic which tell you which part of the LEs is utilized. You'll also consider that a large share of the total transistor count is used for configuration purposes.

Another point to consider is that besides logic elements, also more complex resources like multipliers and memory can be utilized. They are using FPGA transistors much more efficiently, saving in the ASIC translation is respectively lower.

Hi FvM

Yes, I forgot to write "for example..if one stratix V has....".
Sorry I didn't understand your calculation. I am really new in these things. Could you detail me how I can calculate the chip size in the right way using the values I wrote as example? I dont know how you get 0.5x0.5mm. I know that it must be very easy calculation but I didn't understand .
On the other hand, of course I know that there are many factores I have to keep in mind between ASIC and FPGA. However, it is just a littel part of my work and i just know to show simple estimated values.

Thank you so much

Just consider that the 300000 * 800 transistors are arranged in a square matrix. Side length is 15500.

PablodlR said:

One Stratix V has 300.000 ALMs more or less and it uses 28nm TSCM technology. So: 300.000x800x28nm=6.72 m...of course it cannot be possible .

Click to expand...

Your calculation is describing a 28 nm X 6.72 m die, so yeah the number is possible.

To get a calculation that creates a square die.
sqrt(300000 * 800) * 28 = die_side_in_nm. i.e. 434000 nm x 43400 nm or 0.434 mm X 0.434 mm, which is actually far too small by a large margin.

Maybe this will help give you a better idea about transistor counts and the die size that results

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Based on the Intel Intel Sandy Bridge E 6C with 2.27B transistors and a die area of 435 mm^2. It works out for 32 nm process on an Intel fab they need about 191 nm^2 per transistor.

Expecting a transistor size of 28x28 nm (it's quite bit bigger, 28 nm is the structure measure) would result in a 0.5*0.5 mm square chip, duplicate by 5 or 10 and get the correct request of extent…

When meaning ASIC, you'll look to the real LUT use measurement which reveal to you which part of the LEs is used. You'll additionally think about that a huge offer of the aggregate transistor check is utilised for arrangement purposes.

Another point to consider is that other than rationale components, additionally more mind boggling assets like multipliers and memory can be used. They are utilising FPGA transistors substantially more proficiently, sparing in the ASIC interpretation is separately lower.