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port CLASS BUMP in output LEF

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alphus

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Hi all,
I'm implementing IP using Flip-Chip floorplan, so several IO ports must be connected to bumps.
How to set attribute CLASS BUMP in LEF file for several IO ports when writing out LEF (not by hand)?
Now this attribute is "CORE" by default. Tool - cadence Innovus 17.1.
 

Hi all,
I'm implementing IP using Flip-Chip floorplan, so several IO ports must be connected to bumps.
How to set attribute CLASS BUMP in LEF file for several IO ports when writing out LEF (not by hand)?
Now this attribute is "CORE" by default. Tool - cadence Innovus 17.1.

The bump cell itself should come with a LEF file, and in that file the class should be bump. IO ports should not.
 

IO ports should not.

I mean that in the version of LEF 5.7 or greater, port CLASS attribute can be set equal to {CORE | BUMP}.
From "LEF/DEF Language Reference": "BUMP—Specifies the port is a bump connection point. A bump port should only be connected by routing to a bump (normally a MACRO CLASS COVER BUMP cell)"

In other words, how to set this CLASS attribute for some ports of my IP block?
 

I mean that in the version of LEF 5.7 or greater, port CLASS attribute can be set equal to {CORE | BUMP}.
From "LEF/DEF Language Reference": "BUMP—Specifies the port is a bump connection point. A bump port should only be connected by routing to a bump (normally a MACRO CLASS COVER BUMP cell)"

In other words, how to set this CLASS attribute for some ports of my IP block?

I still don't understand what you are doing. IOs from your IP should first go to an IO cell and then be routed from IO cell to bump. I have never seen anyone try to edit an IO to make it a bump class.
 

If IO cell is placed in IP, but BUMP cells are added later by the IP consumer. Thus, IP consumer get an HARD MACRO with 'class bump' attribute on some pins.
 

If IO cell is placed in IP, but BUMP cells are added later by the IP consumer. Thus, IP consumer get an HARD MACRO with 'class bump' attribute on some pins.

That's really unusual.
 

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