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  1. #1
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    ADS-B with FPGA and 'simple' ADC board, is possible? (just for learn stage)

    Hi.

    I'm a developer and electronic hobbyst (PHP, Javascript, C, Delphi, ...), but never used an FPGA before this project. I'm doing my course project and it's an ADS-B receiver based on FPGA.
    I already ordered some boards to play with (One with Artix-7, one with Cyclone IV and one with Spartan-6), all from ALINX. I also ordered one ADC board for testing, this one: ( https://www.ebay.com/itm/AN926-Modul...macf:rk:2:pf:0 ). This is a dual-chanell 12-bits 50MSPS ADC board.
    I already played with Artix-7 board (not mine) at university class, but just LED blinks and some input-checking for turn on/off LED's.

    So I have some questions.....
    1) Can I use this ADC module to develop an ADS-B receiver using FPGA? I'm not talking about best solution/design, but just for developing/learn. I'mm use external filter and LNA for improving signal quality/filtering (ADS-B works on 1090Mhz using PPM signal).

    2) In Arduino and other electronics, I just read ADC value using i2c or other way....in FPGA I know that this module is direct serial connection....it means that the output value are direct send to all 12-pins on FPGA and I must 'build' my value by using all 12 pins values. That's ok......but how do I 'close' (I don't knwo the correct term for this) for only 1090Mhz? That's the logi nand how do I start? I know thatt 1090 is the frequency which values varies from 0 to 1 on wave (not exactly 0 and 1, but kind of), but how do I identify this frequency and ignore other ones? It's the famous FIR digital filter? (i've heard about this and other filters....)? OR am I saying bull***?

    3) Is there any tutorial/example for simple signal identification in FPGA? What I mean for this is: I would like to input some random signal in AD port and FPGA just output an specific frequency (filtered), just to test/learn! I could not find anything 'easy' to learn (just to start).....probabily my mistake, that's why I'm askign for your help.

    4) My board (that didn't arrived yet!) has an 50Mhz clock.....so I guess that all my calculations should be based (or at least use) this clock as source, right? As I learned until now (shich is little), FPGA works all in paralel and I need something to 'trigger' my functions or things that I want to do.....and this 'trigger' is a pin change, for example..... (from clock, external, etc etc...).....is that right?

    I'm sorry if those are dumb questions......but I'm starting with FPGA

    Thanks!

  2. #2
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    Re: ADS-B with FPGA and 'simple' ADC board, is possible? (just for learn stage)

    You'll need an RF front end for your ADC, e.g. pre selection, mixer, IF amplifier. ADS-B bandwidth is quite low, you can receive it with a SDR (software defined radio) solution based on a DVB-T stick like this one http://www.nooelec.com/store/sdr/sdr...smart-sdr.html

    A receiver with dual 50 MSPS ADC and FPGA signal processing allows for much higher bandwidth, but it's not particularly useful for ADS-B. There are however various SDR platforms on the net using high speed ADC and FPGA.



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    Re: ADS-B with FPGA and 'simple' ADC board, is possible? (just for learn stage)

    Hello,

    this is not strict answer, but in my opinion can be useful for you. See in browser "Software Defined Radio" it is very close to what you want to achive. see for example these links:

    https://en.wikipedia.org/wiki/Software-defined_radio

    https://blog.bliley.com/10-popular-s...ed-radios-2018

    https://www.hackster.io/electrobeez/...he-fpga-d35f33

    https://www.rtl-sdr.com/building-ico...defined-radio/

    Regards



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  4. #4
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    Re: ADS-B with FPGA and 'simple' ADC board, is possible? (just for learn stage)

    Quote Originally Posted by FvM View Post
    You'll need an RF front end for your ADC, e.g. pre selection, mixer, IF amplifier. ADS-B bandwidth is quite low, you can receive it with a SDR (software defined radio) solution based on a DVB-T stick like this one http://www.nooelec.com/store/sdr/sdr...smart-sdr.html

    A receiver with dual 50 MSPS ADC and FPGA signal processing allows for much higher bandwidth, but it's not particularly useful for ADS-B. There are however various SDR platforms on the net using high speed ADC and FPGA.
    I already have SDR's based on dongle for ADS-B, but I want to build one based on ADS-B to learn.

    About frontend, I'll use filters and LNA's based on what I already have for my dongles. More espeific, I'll use circuit like ADS-B Cape (Wide-band 1090 filter -> LNA -> Narrow-band 1090 filter -> LNA -> Logaritmic Detector/controller -> ADC): http://ebrombaugh.studionebula.com/r..._schematic.pdf

    What I don't understand (yet) is how do I read this high frequency (1090) since I just have an 50Mhz xtal onboard?
    I know that my signal will be (almost, but not 100%) only my ADS-B data (because of filters, etc...)......but how do I read this with only 50Mhz clock on my board?
    Also, I'm reading a lot of FIR filters....but I don't understand how to apply (or even if is necessary) to my project. I tried with Matlab 2015 Filter Analysis & design, but I can't build bandpass filter for 1090Mhz. Am I on correct way?

    Imagining that my RF frontend is done, what's the next step?

    Since I'm not electronic professional (just hobby!), I'm not sure if I understood correct logaritmic detector/controller.....but here is what I think:
    in 'general way', they get input signal and generate an output 'normalized' signal.....so, if signal is too week on input, they kind of 'amplify' and generate an normalized output.....the same way if signal is too strong, the detector attenuate signal and generate the same normalized (level) output....is this right? (of course, generally speaking!)



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  5. #5
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    Re: ADS-B with FPGA and 'simple' ADC board, is possible? (just for learn stage)

    Did you notice that the "ADS-B Cape" uses a magnitude detector between the 1090 MHz filter and the FPGA? It's effectively an AM receiver.



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    Re: ADS-B with FPGA and 'simple' ADC board, is possible? (just for learn stage)

    Quote Originally Posted by FvM View Post
    Did you notice that the "ADS-B Cape" uses a magnitude detector between the 1090 MHz filter and the FPGA? It's effectively an AM receiver.
    No. Where? and how this works?
    If you are talking about ADL5513, please read my answer/question of this component.

    Tks!

    - - - Updated - - -

    "FvM", the question about magnitude detector remains..... :)

    Now about frequency, I was thinking wrong....
    ADS-B uses PPM for modulation....like this image:
    Click image for larger version. 

Name:	fig1.png 
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    And let's say that I sample my ADC at 20Mhz (and not 50Mhz)....so my minimum detect time is 0.05us.....more than enought to detect/read ADS-B timing, right? Since minimum position for ADS-B bit is 1us/2 (or 0.5us)



  7. #7
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    Re: ADS-B with FPGA and 'simple' ADC board, is possible? (just for learn stage)

    If you are talking about ADL5513, please read my answer/question of this component.
    I don't see a question about ADL5513. But yes, that's the magnitude detector.



  8. #8
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    Re: ADS-B with FPGA and 'simple' ADC board, is possible? (just for learn stage)

    the question is if i'm right about what it does... :)
    I'm not sure if I'm thinking right about this component.....

    "Since I'm not electronic professional (just hobby!), I'm not sure if I understood correct logaritmic detector/controller.....but here is what I think:
    in 'general way', they get input signal and generate an output 'normalized' signal.....so, if signal is too week on input, they kind of 'amplify' and generate an normalized output.....the same way if signal is too strong, the detector attenuate signal and generate the same normalized (level) output....is this right? (of course, generally speaking!)"

    Sorry, read 'weak' instead of week.....



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  9. #9
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    Re: ADS-B with FPGA and 'simple' ADC board, is possible? (just for learn stage)

    A log detector isn't the usual choice for an ASK receiver, but I believe it can work for it.



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