is the race condition normally observed in RC timing analysis?

Hi All

In all my design, it always report something like

Cost Group : 'sclk' (path_group 'sclk')
Timing slack : 6141ps
Start-point : a/b/c
End-point : a/b/c

however, it does not ever report race condition.

Can anyone share some experience?

Thanks

liletian said:

Hi All

In all my design, it always report something like

Cost Group : 'sclk' (path_group 'sclk')
Timing slack : 6141ps
Start-point : a/b/c
End-point : a/b/c

however, it does not ever report race condition.

Can anyone share some experience?

Thanks

Click to expand...

how are race conditions related to timing paths? I fail to see the connection.

sorry, then how the timing tool can detect if there have a race condition?

THanks

liletian said:

sorry, then how the timing tool can detect if there have a race condition?

THanks

Click to expand...

what race condition? where? what are you talking about? do you mean setup violation?

ThisIsNotSam said:

what race condition? where? what are you talking about? do you mean setup violation?

Click to expand...

Yes, I think setup violation is the correct word. How does timing analysis check the setup violation.

Thanks

liletian said:

Yes, I think setup violation is the correct word. How does timing analysis check the setup violation.

Thanks

Click to expand...

https://en.wikipedia.org/wiki/Static_timing_analysis

ThisIsNotSam said:

https://en.wikipedia.org/wiki/Static_timing_analysis

Click to expand...

It looks like hold time violation leads to a Race condition.

how does the timing tool (like rc check the hold timing violation)?

Thanks

Bo

liletian said:

It looks like hold time violation leads to a Race condition.

how does the timing tool (like rc check the hold timing violation)?

Thanks

Bo

Click to expand...

I think you are not ready for the answer judging by your question. Please review the basics of timing, cell propagation delay, setup and hold requirements. These are well covered in textbooks.

As others mentioned question is not making much sense. It is be a good idea to read more about static timing analysis. Feel free to post relevant question if you encounter after that.

In a synthesis-based design flow, first-order timing errors
(internal and fanout loading delays) are fixed during the
optimize-against-constraints cycle.

Post-C-extracted timing simulations can't really be done
well until the entire layout is "done". So a C-only timing
verification will show post-synthesis faults potentially.

RC extraction takes longer to run the more complex netlist
and will show errors (again, potentially) that C-only and
wireload models did not (wireload using only a L based
estimate, perhaps per-layer-segment, lumped but still
unaware of neighbor nets, coupling and branching (R).

Onion, layers, cry, repeat.