Yussef
Newbie level 3
Hello experts,
I would like to know if the clock edge has an impact on clock latency or this later is not related to the clock edges ?
for example if we have a negative level-sensitive latch or flip-flop, and the waveform of the clock signal is {0 5}, so the first falling edge occurred at 5ns. The clock latency will contain 5+propagation delay or just the propagation delay from clock definition point to clock pin of the flip-flop ?
Thanks in advance.
I would like to know if the clock edge has an impact on clock latency or this later is not related to the clock edges ?
for example if we have a negative level-sensitive latch or flip-flop, and the waveform of the clock signal is {0 5}, so the first falling edge occurred at 5ns. The clock latency will contain 5+propagation delay or just the propagation delay from clock definition point to clock pin of the flip-flop ?
Thanks in advance.