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Bottom up synthesis using dc compiler

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Hi All,

I am new to synthesis. I am working on dc compiler. I am trying to do bottom up synthesis .
I have 5 modules, addr, muxsel, counter_dec, counter_inc and top module.
what i know is that, we have to compile all modules individually and then top level.
The design is very basic, just to learn the bottom up approach. The script I have written is shown in the images. The script is not complete. I have some questions:
1. Do i need to store the netlist of all modules?
2. Do i have to compile the top level? if yes how?
3. How to write reports in file? like report_timing, are etc
4. what is characterize command do? when too use this command.
5. And how to debug?

Please help with this.
thanks

Capture.PNG
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1) Yes, you need to write out the ddc or verilog version of each of the submodules that you have compiled.
2) The top level will be a verilog file that instantiates the submodules. The submodule IO will either come from other submodule pins or top level IO pins, this is design dependent
3) Issue the report command and redirect it to an output file: report_xxx > ./filename
 

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