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[SOLVED] Fixing setup violations in RTL

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biju4u90

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There are many posts that deal with setup and hold violations and their fixing in backend stages. Suppose that the initial synthesis itself gives setup and hold violations. What are the possible methods to fix them in RTL?

I could find following suggestions in some of the posts. But how practical are these methods in implementation?
1) Reducing combinational logic delay by minimising the number of logic levels - How is it possible to minimize the number of logic levels without much design changes?
2) splitting the combinational logic - Does this mean that P = A + B + C + D may be redesigned as P = (A+B) + (C+D)? If yes, won't the tool do these sort of optimizations while synthesis?
3) Implimenting Pipelining - This could be a good option. But how tedious will it be to implement pipelining in an already existing design?
4) Using double syncronizer using flipflops - How can double synchronizer fix setup violations?
 

biju4u90 said:
There are many posts that deal with setup and hold violations and their fixing in backend stages. Suppose that the initial synthesis itself gives setup and hold violations. What are the possible methods to fix them in RTL?

I could find following suggestions in some of the posts. But how practical are these methods in implementation?
1) Reducing combinational logic delay by minimising the number of logic levels - How is it possible to minimize the number of logic levels without much design changes?
2) splitting the combinational logic - Does this mean that P = A + B + C + D may be redesigned as P = (A+B) + (C+D)? If yes, won't the tool do these sort of optimizations while synthesis?
3) Implimenting Pipelining - This could be a good option. But how tedious will it be to implement pipelining in an already existing design?
4) Using double syncronizer using flipflops - How can double synchronizer fix setup violations?
Click to expand...

Fixing timing violations in RTL generally means changing your design. As a designer you can come up with a different way that architecturally/functionally will yield same output but uses less qualifiers. This will reduce combinational logic in critical cone. Also you can move logic to previous or next pipe stage (obviously keeping in mind timing margin of prev/next stage and also maintaining functional equivalence). Adding pipestage just mean adding a flop in between. It will delay downstream logic by a clock but if architecture if ok with one clock delay then go for it.
 

swabhi812 said:
Fixing timing violations in RTL generally means changing your design. As a designer you can come up with a different way that architecturally/functionally will yield same output but uses less qualifiers. This will reduce combinational logic in critical cone. Also you can move logic to previous or next pipe stage (obviously keeping in mind timing margin of prev/next stage and also maintaining functional equivalence). Adding pipestage just mean adding a flop in between. It will delay downstream logic by a clock but if architecture if ok with one clock delay then go for it.
Click to expand...

The post above is a good general answer. Some other things to consider:
- hold is not a logic synthesis issue, it's a physical synthesis issue. There is no reason to change RTL to fix hold.
- P = A + B + C + D is equivalent to P = (A+B) + (C+D) . The tools will generate the same logic. What you need is pipelining. P1 <= A+B, P2 <= C+D, P <= P1 + P2.
- I don't understand how you plan to use double synchronizers and how that helps. I think it doesn't.
- You should give retiming a try.
 

3) Implimenting Pipelining - This could be a good option. But how tedious will it be to implement pipelining in an already existing design?
Click to expand...
This process should be your try. See the reply above from ThisIsNotSam.
Why is this tedious?
The tool will exactly tell you where the failure occurs. So just go to the RTL and insert a pipeline stage there.


4) Using double syncronizer using flipflops - How can double synchronizer fix setup violations
Click to expand...
This is used when your data is crossing over from one clock domain to another clock domain.
It does not help to fix violations.
 

ThisIsNotSam said:
P = A + B + C + D is equivalent to P = (A+B) + (C+D) . The tools will generate the same logic. What you need is pipelining. P1 <= A+B, P2 <= C+D, P <= P1 + P2.
Click to expand...

In this case, we are delaying P by 1 clock cycle, right? Suppose this P is used at some other part of the design. Won't this break the existing logic? Or you mean to say that, while applying pipelining, we should be taking care of this situation also?

- - - Updated - - -

dpaul said:
This process should be your try. See the reply above from ThisIsNotSam.
Why is this tedious?
The tool will exactly tell you where the failure occurs. So just go to the RTL and insert a pipeline stage there.
Click to expand...

Please see my above comment. Won't this make inserting pipelining a tedious process in an existing design?
 

Yes it is tedious to add pipelining after the fact, that is why good designers think about the amount of logic they are building between pipeline stages when they intially design a module and seldom have to manually add more pipelining when they are nearing layout.
 

Suppose this P is used at some other part of the design. Won't this break the existing logic? Or you mean to say that, while applying pipelining, we should be taking care of this situation also?
Click to expand...
Create a separate instance!
 

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