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    SPI verilog testbench code

    Hi, I found it strange to have "backend" interface for a SPI master verilog code. Could anyone comment about its necessity in simulation or formal verification ?


    lattice SPI application note



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    Re: SPI verilog testbench code

    What exactly do you find "strange" about it? Its the way you drive the SPI interface for this implementation.



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    Re: SPI verilog testbench code

    For actual hardware testing, I do not think it is necessary to write a backend interface when the slave itself is a SPI flash since the flash already had this backend interface internally.

    However for simulation, I believe this backend interface is still needed ??



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    Re: SPI verilog testbench code

    How do you expect to drive data into our off the spi bus without the backend. Why do you want to removed it anyway?



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    Re: SPI verilog testbench code

    should I hardcode my SPI flash instruction in FPGA hardware logic or use a SPI linux driver ?



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    Re: SPI verilog testbench code

    Linux driver every time.



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    Re: SPI verilog testbench code

    I have included the backend interface for the master (FPGA) flash controller.

    However, I am not sure how to simulate this correctly ? There is no physical SPI flash that I can simulate with in computer. Do I really need a verilog simulation model of the SPI flash device itself ?

    My Winbond W25Q32FV SPI flash does not provide any verilog simulation model that I can use

    Code Verilog - [expand]
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    module SPI(clk, reset, data_valid, data_MOSI, data_ready, data_MISO, MISO, MOSI, clk_flash, CS_flash);
     
    parameter MOSI_DATA_BITWIDTH = 8;
    parameter MISO_DATA_BITWIDTH = 8;
     
    input clk, reset;
     
    input data_valid;
    input [MOSI_DATA_BITWIDTH-1:0] data_MOSI; // data going into the slave (SPI flash)
     
    output reg data_ready;
    output reg [MISO_DATA_BITWIDTH-1:0] data_MISO; // data originating from slave (SPI flash)
     
    input MISO;
    output reg MOSI;
    output clk_flash;
    output reg CS_flash;
     
    reg [($clog2(MISO_DATA_BITWIDTH)-1):0] in_index;
    reg [($clog2(MOSI_DATA_BITWIDTH)-1):0] out_index;
     
    assign clk_flash = clk;
     
    always @(posedge clk)
    begin
        if(reset) begin
            CS_flash <= 1;
        end
     
        else begin
            if(data_valid) CS_flash <= 0;  // new SPI flash transaction
     
            else CS_flash <= 1;  // SPI flash transaction finished
        end
    end
     
    always @(posedge clk)
    begin
        if(reset) begin
            MOSI <= 1;
            out_index <= 0;
        end
     
        else begin
            MOSI <= data_MOSI[out_index];
            out_index <= out_index + 1;
        end
    end
     
    always @(negedge clk) // this SPI flash sends out its data on the falling edge, so this flash controller has to follow SPI flash spec
    begin
        if(reset) begin
            data_ready <= 0;
            data_MISO <= 0; // all zeroes
            in_index <= 0;  // the shift register 'data_MISO' stores the data starting from LSB
        end
     
        else begin
            if(in_index == MISO_DATA_BITWIDTH) begin
                data_ready <= 1;  // data collection from slave is complete or finished now
                in_index <= 0;
            end
     
            else begin
                data_ready <= 0;
     
                if(CS_flash && !data_ready) begin // collect data from slave (SPI flash) during the transaction
                    data_MISO[in_index] <= MISO;
                    in_index <= in_index + 1;
                end
            end
        end
    end
     
    endmodule
    Last edited by promach; 9th November 2018 at 05:02.



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