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Verilog to schematic simulation not working, please help

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michael_mikhael

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I followed some tutorials to create symbol and schematic from Verilog but when I simulate the schematic I get nothing in the output, I checked the the circuit a bunch of times and repeated the whole thing also a few times but it still doesn't work

Screenshot-17.png

Screenshot-18.png
 

No idea how the question is related to Verilog because you are showing an analog simulation circuit. The vdd and vss connection is however obviously wrong. You want connect vss to ground and vdd to a positive dc voltage.
 

nothing, when I descend in the hierarchy I don't see the transistors
 

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