RF vs VDD Pad Design Techniques

Hello,

I am doing and RF IC layout and need to make my own pads as the PDK does not include them.

For the RF I/O pads I just but a top metal pad and nothing else while for the RF Gnd pads I stacked all the metal layers to my chosen ground plane.

Now for the Biasing pads ie. VDD and VDD Gnd, can I just use a stack of a metal layers again for these DC pads ?

Are there any resources, ie papers, etc that describe these considerations.

Thank you.

Your RF pad may be a problem. Check your design rules and make sure the pad does not require metals/vias underneath the pad metal. Also, run DRC to make sure you haven't missed anything.

It will not pass the drc rule if you only use top metal as the pad.

Ok, so what should I do then ?

You can use metal 1 to the top metal stacked together. No worry about the noise, since there is no diffusion layer under the metal 1. No noise coupled.

A single top metal layer may or may not be up to the
assembly process (bond pull strength, pad peeling etc.).
The right outfit to talk to is your planned assembly house,
who should have some set of pad rules (but this may be
X-Y only, depending on experience / diligence / customer
base / inspection regimes).

There could be compromises such as using (say) Met5,
Via5, Met6 rather than Met6 alone, if things like bond
push-through amd adhesion are issues for the simplest
scheme. Lose 20% of under-pad ILD hight but gain
50-100% pad metal thickness, like.


Your foundry probably also has someone who knows the
"why?" about pad construction and could tell you whether

- a similar pad design has been seen, waivers granted,
and any subsequent assembly reliability results, though
this latter might be proprietary to the customer; might
be you could get a contact

- any special underlayer features are "semi supported"
(like quiet-grounded Nwell pockets, noise guardrings,
etc.)

- What's the "done thing" re ESD protection, the trade
between HF losses / pin Z match and handling ESD level