FPGA implimentation of a pulse divider circuit

Hi,
Iam a newbie in FPGA world. I have experience in PLC's and Arduino microcontroller. I want to develop a system which takes an incremental encoder output as input and will be able to count up/down. The system must be capable of giving specific number of pulses when the above count reaches a specific value. All these values will be specified by setting variables inside memory via tcp communication.
For implimenting this, where to start with?. Which FPGA/microcontroller should I use?. The problem with arduino is that the microcontroller misses some pulses and the whole process go wrong. Iam assuming that if we impliment this logic in an FPGA, it will not be affected by other logic additions in the same IC. The frequency of the pulses may go upto 1Mhz.
Kindly advise

A microcontroller with quadrature encoder interface (e.g. dsPIC30/33, some PIC18 and PIC24, many ARM processors) can easily process 1 MHz pulse rate.

Hi,

an incremental encoder with 1MHz pulse rate... are you sure?
What interface does it use.?

Klaus

The problem with arduino is that the microcontroller misses some pulses

Click to expand...

If the encoder always rotates in the same direction, you can use the one-channel counting trick, which is certainly not an accurate solution, particularly because it would reduce the counting resolution from 1:4 ratio along with the fact that when the system is "stopped" and a wobble occurs due to mechanical trepidation in the vicinity, it could erroneously indicate a non-existing movement.

But if you want something a bit more robust without having to migrate from current platform, though admitting loss of resolution, you can also use a small external logic so you can count these pulses by the capture counter feature of the timer:






Reference:
https://www.edaboard.com/showthread...ptical-encoder&p=921425&viewfull=1#post921425