Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
DRC should check for this. Maybe you've got that check turned off. You don't say what tool you're using. Depending on your board house you may end up with ink on your via. Or not.
DRC may check it, more commonly unwanted silk screen elements conflicting with exposed copper or drills are cut in post process or by the PCB manufacturer. But unlike silk screen on top of pads, silk screen over vias doesn't actually hurt.
Usually the vias are covered by solder mask and silk screen is on top of that. I do not think silk layer will cause any issue with vias.
But if it is a component pad or a pin, there may be some interference in soldering. In particular, if the silk screen is directly on top of exposed copper.
What is the specific problem you are thinking about?
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.