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Does silk layer cause issues for vias

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Zak28

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What happens if you submit a board for fabbing with silk covering a via or some other hole?

The DRC doesn't seem to check for this issue.
 

DRC should check for this. Maybe you've got that check turned off. You don't say what tool you're using. Depending on your board house you may end up with ink on your via. Or not.
 

DRC may check it, more commonly unwanted silk screen elements conflicting with exposed copper or drills are cut in post process or by the PCB manufacturer. But unlike silk screen on top of pads, silk screen over vias doesn't actually hurt.
 

silk covering a via or some other hole

Usually the vias are covered by solder mask and silk screen is on top of that. I do not think silk layer will cause any issue with vias.

But if it is a component pad or a pin, there may be some interference in soldering. In particular, if the silk screen is directly on top of exposed copper.

What is the specific problem you are thinking about?
 

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