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  1. #1
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    data and clock synchronization using 74HC4046 PLL

    I am using HDB3 decoder IC for HDB3 to TTL/NRZL convertor.
    for synchronization I need to use 74HC4046 PLL IC.

    Input frequency is 2.048MHz
    output should be the same 2.048MHz.

    can anyone help me in this regard to select R1, R2 and C1.
    and the rest of the components value related to VCO input.


    Even in Proteus simulation this
    IC is not working properly.

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    Re: data and clock synchronization using 74HC4046 PLL

    Hi,

    the datasheet gives a lot of information about the ranges and the typical frequencies for R1, R2 and C1.

    But the datasheet can´t know your requirements.
    We don´t know them either.

    I assume you have to decide them first.

    Klaus
    Please don´t contact me via PM, because there is no time to respond to them. No friend requests. Thank you.



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    Re: data and clock synchronization using 74HC4046 PLL

    Which signal are you feeding to the 4046 PLL? I don't think that the phase/frequency detector is suited for clock recovery from HDB3 coded signal.



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    Re: data and clock synchronization using 74HC4046 PLL

    Actually I feed CRX from HDB3 decoder IC (CD22103A) to 74HC4046.
    the frequencyis 2.048MHz.



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    Re: data and clock synchronization using 74HC4046 PLL

    Actually I feed CRX from HDB3 decoder IC (CD22103A) to 74HC4046.
    the frequency is 2.048MHz.
    How? CRX is an input at CD22103A. Datasheet says "requires clock recovery circuit". Thus I thought you want to use 4046 for clock recovery, which isn't feasible.

    https://www.intersil.com/content/dam...2/cd22103a.pdf


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    Re: data and clock synchronization using 74HC4046 PLL

    Sorry Mistake
    Clock required for CRX from CKR
    as @ FvM said Clock recovery circuit.

    Actual scenario will be HDB3 data feed to CD22103A input lines. CKR signal (used for clock recovery circuit) feed to 74HC4046
    and 4046 output feed to CRX for synchronization.

    data rate of HDB3 line is 2.048MHz



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    Re: data and clock synchronization using 74HC4046 PLL

    Do you have any references that 4046 is suited as clock recovery circuit for input signals similar to CKR? I fear it isn't.



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    Re: data and clock synchronization using 74HC4046 PLL

    I got this scheme from the following link
    members.home.nl/frankpol/documents/Phase%202-%20FINAL.pdf



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    Re: data and clock synchronization using 74HC4046 PLL

    The report states that 4046 is used for clock recovery but doesn't give any details, e.g. which phase detector (1, 2 or 3) is used and if 4046 needs support by additional hardware to perform clock extraction.

    As far as I understand, PD 1 or 3 may work, not PD2 (actually a PFD). VCO frequency range must be restricted to a small range around 2.048 MHz to avoid locking to a wrong frequency.


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    Re: data and clock synchronization using 74HC4046 PLL

    Thank you @ FvM.
    do you have any other idea for clock recovery circuit.
    I tried PLL IC, but its not working yet.
    can you help to estimate the parameters for PLL or Proteus simulation ?



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