Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Multi-vth design not performed

Status
Not open for further replies.
O

onta00

Newbie level 4
Joined
Oct 11, 2018
Messages
5
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
33
I’m trying to implement my design using two libraries, one containing cells with low threshold voltage, and the other one with high threshold voltage, in order to minimize the leakage power. I included them in the link library and target library, but at the end of the process, design compiler has used only cells of the library with higher threshold voltage. Why? Did I miss something to allow dc using both libraries ?
 

Did you have set
set_scenario_option -leakage_power true
or
set_leakage_optimization true
 

oratie said:
Did you have set
set_scenario_option -leakage_power true
or
set_leakage_optimization true
Click to expand...

yes i used set_leakage_optimization true, but the result is the same
 

if you have any scenarios defined, you should use set_scenario_option.
 
  • Like
Reactions: onta00

    O

    onta00

    Points: 2
    Helpful Answer Positive Rating
The fact is I have no scenarios set
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top