shragh
Newbie level 3
Hi,
After performing CTS with IC Compiler, I get a list of max_capacitance violations on all the clk pins of the macros in my design.
I found out from the logs that the problem is because the clock inverters with higher drive strength (X12, X16, X20) are pruned by the tool (the message says they are pruned due to a gain of *some value*), and hence not used for DRC fixing. As a result, even the clk inverter with the highest drive strength used has an output max capacitance lower than the load capacitance of the macro clk pin.
According to Synopsys documentation, this pruning appears to be out of the user's control. Has anyone faced this issue? If so, is it a good idea to avoid all clk inverters and go with only clk buffers? Or is this maxcap violation something that can be ignored?
Thanks,
After performing CTS with IC Compiler, I get a list of max_capacitance violations on all the clk pins of the macros in my design.
I found out from the logs that the problem is because the clock inverters with higher drive strength (X12, X16, X20) are pruned by the tool (the message says they are pruned due to a gain of *some value*), and hence not used for DRC fixing. As a result, even the clk inverter with the highest drive strength used has an output max capacitance lower than the load capacitance of the macro clk pin.
According to Synopsys documentation, this pruning appears to be out of the user's control. Has anyone faced this issue? If so, is it a good idea to avoid all clk inverters and go with only clk buffers? Or is this maxcap violation something that can be ignored?
Thanks,