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  1. #1
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    Fatal error while running top module || UVM

    Hello!
    I am trying to run my first UVM design using these command but I get those errors
    Click image for larger version. 

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    And the commands(these commands used after compiling the design file and UVM files)
    Code:
    vlog AES_MoniterAFter.sv -dpiheader dpiheader.h  add.c
    vsim  -coverage -t 10ns -novopt work.AES_tb_top +UVM_TESTNAME=AES_test set NoQuitOnFinish 1
    onbreak {resume}
    log /* -r
    run -all
    Is something wrong with these commands or the UVM design has an error?
    Thanks..
    Last edited by ranayehya; 13th October 2018 at 18:54.

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  2. #2
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    Re: Fatal error while running top module || UVM

    Do you have
    Code Verilog - [expand]
    1
    2
    3
    
    class AES_test extends uvm_test;
    `uvm_component_utils(AES_test)
    ...
    somewhere?
    Dave Rich
    Senior Verification Consultant
    Mentor Graphics Corporation



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  3. #3
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    Re: Fatal error while running top module || UVM

    Yes, I have. Sir, Dave Rich.
    Do you want to see the code ?



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  4. #4
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    Re: Fatal error while running top module || UVM

    Is that class in your AES_MoniterAFter.sv file? If not, how do you expect vsim to find it?
    Dave Rich
    Senior Verification Consultant
    Mentor Graphics Corporation



  5. #5
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    Re: Fatal error while running top module || UVM

    AES_MoniterAFter.sv file's job is to import a C code and predict the output. AES_test is in top module(the interfacing module between UVVM files and verilog code). I already compiled the top module.

    - - - Updated - - -

    I found my problem. I declared two variables with the same name + "r" in one of them. I am sorry for my bad naming and bothering you.



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