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What is going on with my D flip-flop in Hspice?

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Amamiya_Ren

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When clk is high, the change of D should not affect the output Q, but in my circuit, Q changes with D. I am using bsim-cmg model. Here is the netlist and wave8-O. 1539351083(1).png1539351156(1).png
 

Yeah, but I think this circuit is a dff_20181012215134.jpg
 

The circuit is a level triggered D-latch, not an edge triggered DFF, see the below schematics for differences. The behavior is as expectable.

D-Latch.PNG

DFF.PNG
 
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