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  1. #1
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    What is going on with my D flip-flop in Hspice?

    When clk is high, the change of D should not affect the output Q, but in my circuit, Q changes with D. I am using bsim-cmg model. Here is the netlist and wave.Click image for larger version. 

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ID:	149503Click image for larger version. 

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  2. #2
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    Re: What is going on with my D flip-flop in Hspice?

    Quote Originally Posted by Amamiya_Ren View Post
    When clk is high, the change of D should not affect the output Q, but in my circuit, Q changes with D. I am using bsim-cmg model. Here is the netlist and wave.Click image for larger version. 

Name:	1539351083(1).png 
Views:	3 
Size:	84.9 KB 
ID:	149503Click image for larger version. 

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Size:	45.1 KB 
ID:	149504
    looks like you implemented a latch
    Really, I am not Sam.


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  3. #3
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    Re: What is going on with my D flip-flop in Hspice?

    Yeah, but I think this circuit is a dffClick image for larger version. 

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ID:	149505



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  4. #4
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    Re: What is going on with my D flip-flop in Hspice?

    The circuit is a level triggered D-latch, not an edge triggered DFF, see the below schematics for differences. The behavior is as expectable.

    Click image for larger version. 

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    Click image for larger version. 

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ID:	149507


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