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  1. #1
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    One clock cycle delay for the input data

    Hi all, I am new to digital design. shown in the figure there is an 'addr' signal which is generated by some state machine. I want to sample the input data 'data_rec_in' with one clock cycle delay. Below is the code for the block.



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  2. #2
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    Re: One clock cycle delay for the input data

    Hi,

    usually just a (additional) DFF is used to delay by one clock cycle.

    Klaus
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