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Problem with IR2112 on Proteus

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hdrdiab

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Hello,

I am designing a pure sine wave innverter and am using IR2110 as a driver for the H-bridge. On protues however only IR2112 is available so i used it. I managed to get all the connections in a correct way with a good value for the bootstrap capacitor. However i am always getting a distorted signal on the output of the h-bridge(pic is below). I changed my spwm code and still the same. I am using pic16f877A with 32 values for the sine string.The generated spwm freq. is 16kHz. The clock frequency of the uC is 16MHZ Any ideas why this could happen?

Screenshot (24).png
 

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Your waveform resembles a correct sine PWM to a resistive load, but unsmoothed by a low-pass filter. Because it covers an entire AC cycle, with positive polarity, then negative polarity.

If you add the usual LC second-order filter then you can expect a sinewave at the load.

- - - Updated - - -

Now I see the LC arrangement is at bottom left of your schematic. The values appear correct. But no load is present. A load needs to be attached, so that current goes through the filter. Then you should see a sinewave across C11.

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Therefore move R11 so it is across C11.
 
hello,
I am actually getting a sine wave output but i was wondering if making the output of the H-bridge look like this(pic below) could get me better signal. Shouldn't the output of the H-bridge be like this:Untitled.png
 

Yes, the LC arrangement is able to shape pulses into a sinewave.
It can shape a plain AC square wave into a sinewave.
You can also put the LC in series.
Henry and Farad values need to be customized to suit frequency, voltage, load.

It is important to correct for power factor error, so that Ampere waveform through the H-bridge aligns with applied voltage. The L value has the chief influence. Greater L causes current to lag voltage, as well as reduces current. With a simulator we can see the result of various L & C combinations.
 

Problem is probably an inappropriate PWM pattern. Seems like you are switching either B or D on and off. This pattern can only work for a purely resistive load, but not with an LC filter. For reactive load, there must be no free-wheeling phase with high and low-side transistors off.

Read about two-level and three-level PWM schemes. You can apply two level pattern by switching between B and D. Preferred three-level pattern needs different gate driver wiring.
 
The low resolution of the attached image do not make things very clear, but apparently you are using a cosine table instead of a sine, or maybe you are simply switching the polarity of the bridge at the wrong time, offset by 90 degrees.
 

According to the schematic and oscilloscope settings, the yellow waveform is showing the difference between both bridge outputs. You would expect a three level wave as shown in post #3, but the bridge output is apparently not switching as expected, particularly not falling to zero. The average value should represent a sine after filtering, but it isn't displayed in oscilloscope. You can conclude that incorrect switching must result in an incorrect average output.

I explained why the gate drive pattern can't achieve correct switching with reactive load.
 
The output is not a perfect sine wave, it have a flat top, if i try to tweak the filter and remove the flat top i get a voltage drop. I managed to get an output of the H-bridge like the one in post #3 and that is by removing the grounds from the pins of the gate drivers so the COM and SD pins of the drivers are not connected to anything,however i am getting a dramatic voltage drop at the output. Can you suggest any solutions should i look for another way or method. I am sure of my spwm signals i tried more than one way for generation and still same result.
 

You didn't show the used PWM pattern. Can you sketch it or show the respective Proteus waveforms and explain why you selected it this way, e.g. with literature reference.
 

Below are my driving signals, red high side left , green low side left, blue high side right, yellow low side right. Almost every place i searched uses these signals for the drivers. These spwm signals contain the 50HZ fundamental frequency and the H-bridge only have to combine the two spwm signals (which are 180 degrees out of phase) in a unipolar scheme. Ill give some links below:

https://tahmidmc.blogspot.com/2012/10/generation-of-sine-wave-using-spwm-in_10.html

https://tahmidmc.blogspot.com/2013/01/using-high-low-side-driver-ir2110-with.html


Screenshot (27).png
 

Simulation showing SPWM waveforms with 1 kHz carrier. Each pulse goes all the way to the zero line, for the reason that the component models are ideal. Notice my load gets similar waveforms as yours.

SPWM 2 opamps drive H-bri Nmos Pmos 30V resis load no filter.png

Your waveforms are more similar to real life. Your brief pulses make only partial transition (creating the shape of an arch). Probably due to some capacitive or inductive influence. If you were to slow your carrier frequency then the pulses will have more time to fall to zero, including the very brief pulses.
 
Post #10 shows a useful unipolar (three-level) scheme, although the assignment of high and low side signals is partly confused. The schematic in post #1 is however not according to this scheme by connecting only B and D signals.
 
Yes, in post one i was trying to use only the spwm signals. Actually i am getting the same results from both ways(using B,D or using ABCD). So should i just pass on this simulation and go to hardware to see results?
 

The H-bridge creates AC at the load by acting like a buck converter in one direction, then it turns around and acts like a buck converter in the opposite direction.

Your controller turns the mosfets On and Off in such a way to duplicate the action of a buck converter. By means of SPWM or by means of uniform pulses.
 

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