SYNOPSIS - Clock creation and delivery to submodules

[kls213]

Hi Everyone,
I'm trying to synthetize my circuit composed by several submodules and I've created a clock using <create_clock -name "CLK" -period 5 CLK> in my very top level, but when i go inside a submodule and go to check the clock there the shell says that the current design has no clock constrain, as it is not connect from the top level. Should I create a clock for each submodule or is this behavior normal?

thank to everyone

[dpaul]

Should I create a clock for each submodule or is this behavior normal?

No, clock constraining should be done at the top module.

1. Have you simulated your design correctly?
1. Recheck you constraining.
3. For more help the constraint file commands will be needed.

[kls213]

No, clock constraining should be done at the top module.

1. Have you simulated your design correctly?
.

Yes, I mean when I simulate before the synthesis circuit works correctly. Also when I try to <report_clocks> from the top level it gives the name of the clock that I've created before, but when I write in dc_shell:

<current_design 'mySubModule'> 
<report_clock>

it says that no clock is present

[arvinraj]

Hi kls,
Current design basically "switches" to another design, and does not go deeper into the hierarchy. What you should be using instead is "current_instance top/hier_you_are_interested/module"