kls213
Newbie level 2
Hi Everyone,
I'm trying to synthetize my circuit composed by several submodules and I've created a clock using <create_clock -name "CLK" -period 5 CLK> in my very top level, but when i go inside a submodule and go to check the clock there the shell says that the current design has no clock constrain, as it is not connect from the top level. Should I create a clock for each submodule or is this behavior normal?
thank to everyone
I'm trying to synthetize my circuit composed by several submodules and I've created a clock using <create_clock -name "CLK" -period 5 CLK> in my very top level, but when i go inside a submodule and go to check the clock there the shell says that the current design has no clock constrain, as it is not connect from the top level. Should I create a clock for each submodule or is this behavior normal?
thank to everyone