gauravsharma93
Newbie level 3
icc_shell> verify_pg_nets
Cell cont.err existed already. Delete it ...
Using [2 x 2] Fat Wire Table for M1
Using [2 x 2] Fat Wire Table for M2
Using [2 x 2] Fat Wire Table for M3
Using [2 x 2] Fat Wire Table for TOP_M
Checking [VSS]:
There are no floating shapes
ERROR: There are 13 floating pins
Checking [VDDO]:
There are no floating shapes
All the pins are connected.
No errors are found.
Checking [VSSO]:
There are no floating shapes
All the pins are connected.
No errors are found.
Checking [VDD]:
There are no floating shapes
ERROR: There are 13 floating pins
Checked 4 nets, 2 have Errors
Update error cell ...
1
icc_shell>
Can any one help me?
I have connected the IO PADS in verilog netlist generated from Design Compiler. But i dont know how to connect power pads as there is a lvs error shown above
Cell cont.err existed already. Delete it ...
Using [2 x 2] Fat Wire Table for M1
Using [2 x 2] Fat Wire Table for M2
Using [2 x 2] Fat Wire Table for M3
Using [2 x 2] Fat Wire Table for TOP_M
Checking [VSS]:
There are no floating shapes
ERROR: There are 13 floating pins
Checking [VDDO]:
There are no floating shapes
All the pins are connected.
No errors are found.
Checking [VSSO]:
There are no floating shapes
All the pins are connected.
No errors are found.
Checking [VDD]:
There are no floating shapes
ERROR: There are 13 floating pins
Checked 4 nets, 2 have Errors
Update error cell ...
1
icc_shell>
Can any one help me?
I have connected the IO PADS in verilog netlist generated from Design Compiler. But i dont know how to connect power pads as there is a lvs error shown above