Unable to grab PCIe ref_clk for the axi_pcie in ZC706 board !

Dear all,


I am working with Vivado 2017.2 targeting a ZC706 ZYNQ FPGA Board operating on an Ubuntu 16.4 Linux Machine.


Previously targeting a Kintex-7 KC705 Board, I was able to choose the PCIe_refclk as the input clock of the buffer in vivadoblock design and use it as the clock signal in my design. Indeed, by double-clicking on the Utility Buffer IP, I had the option to connect the CLK_IN_D pin of the buffer to the PCIe clock.


Recently, I have migrated to ZC706 which includes a XC7Z045FPGA. While this FPGa has the PCIe and GTx channel, I do not see the PCIe_ref_clk available in the board file (board options) and also the lspci command in terminal does not ercognize the ZC706 board while it is connected to the motherboard's PCI bus and also the system was restarted!


I also verified these links (link1, link2) and found nothing helpful!

Did anyone experience this problem before to help me to solve this issue?



Thanks,

Daryon,

I have some experience in creating the board, pins and preset files (XML files).
My first fought is to install latest Vivado 2018.2.1 (even if you don't have a license) and check if the board definition for ZC706 is in higher version then in 2017.2 (check Vivado/data/board folder). If yes, then copy that folder into your Vivado version (2017.2).