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[SOLVED] Design an RTL for different FPGA types compliance

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manili

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Hello all,

I'm wondering to know if it is possible to design an RTL which is acceptable for different types of FPGAs (excluding the resource volume restrictions)?
For example, What would happen if I do not use any sorts of hard-cores and soft-cores? Now, is it possible to synthesize my RTL for both "Cyclone series" and "Virtex series" without any changes (using Vivado and/or Quartus)?
What would happen if I only use soft-cores? Is the design going to synthesize only on the platform which has the IP core?

Thanks a lot.
 

I guess the short answer is NO.
The longer answer is: it depends.

Hard cores will be specific to a chip, and wont be portable.
Soft IPs are usually portable within a manufacturer, unless they are locked to specific series. So things like BRAMs or Altsync rams should compile for multiple families (within Altera/Xilinx) assuming you havent used any family specific features.
IP you build yourself can be portable across several vendors and several families, if you code it in a way that is acceptable to all.

But you are most likely unable to port an entire project, as it will likely a combination of the above.
 
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    manili

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Thanks for your reply @TrickyDicky:

So that's why we have to add many changes to almost every single IP core hosted by the OpenCores website?
 

If the author has used a load of generated IP in their design, then yes, you will need to do lots of changes if you are using a different family or vendor.
Honestly, most stuff on opencores is made by hobbiests, often without good HDL or design skills.
Most businesses tend to ignore stuff from opencores and either Buy the IP themselves or roll their own.
 
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yes, also half of opencores is gpl.
 

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