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    Loop Gain Phase issue for the OpAmp with Class AB output stage

    Hi,

    I am confused about the phase shift at DC for the stb analysis of a Class AB op amp shown in figure below. Please note the input and output polarity.

    Click image for larger version. 

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    I put the op amp in negative feedback as inverting configuration below

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    If I do the DC sweep with same R value (R1 = R_fb = 10k) the dc output sweep is expected, shown below

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    But, If I do stb analysis I see that at DC the phase shift is around 0, figure below

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    I expect 180 degree phase shift at the beginning of DC, not sure why I am not getting that. anybody could explain please? FYI, I also get the transient behavior as expected.

    Thanks in advance.
    Your life is all about ΔΣ, the narrow you estimate it, the precise it is ...

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    Re: Loop Gain Phase issue for the OpAmp with Class AB output stage

    I am happy not only my Cadence is doing things which are nonsense. I also experienced this, with a similar rail-2-rail class-AB OPAmp, very strange behaviour.
    However I couldn't explain it yet in 100%, the present situation or conclusion is that it is not a problem, only appears in AC and STB analysis, and next to certain input variable conditions (stability parameters are still fine, transient oscillation doesn't appear) and probably it is only a modelling issue.
    For example, if you run PVT corners probably the phase will start from 180° in some of them, or if you change the load, or change input common mode DC level, etc.
    Other strange thing which you can experience is the DC gain can rapidly increase with certain resistor load values and with different input/output DC levels.

    I figured out finally that this circuit's speciality, the floating current sources (or Monticelli class-AB biasing) cause these, and interesting that the BULK effect of the floating current source.

    Try to connect the biasing diode's BULK to its SOURCE on the NMOS and PMOS side, and connect the BULKs on the floating devices to the SOURCE too, so quiescent current in the output stage won't change, but probably the phase will start from 180° as it should in every PVT corners, with any load and every DC level.

    I am not sure about the exact reason and this solution, I didn't have enough resources to check every operating parameters, but I know it solved.
    Please won't hesitate to write if you know anything about this.
    "Try SCE to AUX." /John Aaron/


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    Re: Loop Gain Phase issue for the OpAmp with Class AB output stage

    Hi Frank, Yes it is working expected with source-bulk shorted. But the DC gain decreases indeed, around 20 dB!
    Your life is all about ΔΣ, the narrow you estimate it, the precise it is ...



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  4. #4
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    Re: Loop Gain Phase issue for the OpAmp with Class AB output stage

    I would say if you have 90dB gain that isn't bad in typical case. However if you need more, try the usual methods to improve it, like increase current-source length to decrease the gm and increase output resistance, or increase the width of the differential pairs, try to add some gain boosting, etc.
    The floating current mirror is a tricky animal, normally it should connect the drains of the NMOS and PMOS cascode devices like a piece of wire from an AC terminology, but it has its own feedback so can create more than expected. I wouldn't play with it to change gain.
    "Try SCE to AUX." /John Aaron/



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