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Power Measurement Error with Design Compiler?

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mumichang

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Hi, all.

I have measured the power of a verilog module (simple booth multiplier) by using dynamic activities data and dc_compiler. With SAED90nm from TSMC, a reasonable power value is obtained. However, with SAED32nm, very small dynamic power is obtained. Especially, zero cell internal power does not look okay.

Cell Internal Power = 0.0000 uW (0%)
Net Switching Power = 19.6509 uW (100%)
---------
Total Dynamic Power = 19.6509 uW (100%)
Cell Leakage Power = 97.3580 uW

Any suggestions about where to start fixing this problem?
 

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