Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

[SOLVED] OTA Open Loop Gain and Phase Margin

Status
Not open for further replies.

styxies

Junior Member level 1
Joined
Aug 30, 2018
Messages
16
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
109
Hi all, I am trying to design an OTA, and I was checking it's phase margin and open loop gain, using the attached test bench,

However, my obtained gain is negative. Around -40 dB. is my test bench wrong? How can I improve it?

Thanks.


Attached is the test bench and the resulting gain and phase plots.


Screenshot-2.png

Screenshot-3.png
 

Annotate the device operating points, check your devices are in the saturation region.
How much is the output resistance of your OTA? Are you sure the 100kOhm is high enough to generate DC feedback compared to Rout?
 

Even when I increase the resistance, it still results in negative dB gain.
 

Sounds like an op problem?
 

what do you mean? There's something wrong with my OTA?
 

The test bench looks flawed, there's no DC feedback in effect, the feedback path is shorted by the input sources.
 

The test bench looks flawed, there's no DC feedback in effect, the feedback path is shorted by the input sources.

Hi, any suggestions on how to improve it?
 

You designed an OTA so if the transconductance is ok you shouldn't worry about the voltage gain. However if the load resistors don't affect the voltage gain, probably your devices will operate in a wrong operating point. Check them.
 

You designed an OTA so if the transconductance is ok you shouldn't worry about the voltage gain. However if the load resistors don't affect the voltage gain, probably your devices will operate in a wrong operating point. Check them.

Unfortunately, I need to have the open loop gain plot to have the gain bandwidth. This OTA is to be then used for a gm-c filter
 

Unfortunately, you still need the transconductance vs. frequency plot for a Gm-C filter with the respective capacitive load. Not the voltage gain.
 

Unfortunately, you still need the transconductance vs. frequency plot for a Gm-C filter with the respective capacitive load. Not the voltage gain.

Ok thanks. I will also try obtaining this waveform.
 

Hi all, is it ok for the DC gain to be negative dB?
 

is it ok for the DC gain to be negative dB?
Not at all. An amplifier with DC gain below unity would be useless. In this case, the number indicates that you didn't manage to achieve a useful operation point in the test setup.
 

Not at all. An amplifier with DC gain below unity would be useless. In this case, the number indicates that you didn't manage to achieve a useful operation point in the test setup.

Hi, thanks for the reply, do you have any suggestions how I can improve my test setup?
 

what is your amplifier. What I see here is just a block.
Could you show your amplifier ? and do DC annotation.

Also you AC setting is not appropriate.

Set AC voltages to be -0.5 and +0.5
 

Hi All!

I finally found the problem. Me being the inexperienced designer that I was, simulated the circuit together with the CMFB circuit inside. Which meant I had resistors connecting both my outputs and then was connected to a sense amp. When I simulated separate the OTA and the CMFB, the issue was resolved.

I also modified the testbench based on the testbench from Baker's book. Attached here. Thank you all!

This screenshot is from Baker's CMOS Circuit Design, Layout and Simulation book page 798.


Screenshot-7.png
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top