CMOS inverter output ?

Hi all,

I have two questions regarding CMOS inverter output.

1) When the Vdd is off and my input to inverter is still present (0 or 1). what is the output.
I think it gives X, but dont know how.


2) When Vdd is applied but my input is X. In this scenario what is the output?

Please help. would appreciate.

Thanks

Hi,

it depends on the device you are using.

For usual logic ICs (HC, HCT...) you must not give HIGH signal to an unpowered device. --> read the datasheet
But other families like AHC, AHCT will can widthstand HIGH signal when not powered. --> Read the datasheet. (also about output signal when not powered)

Klaus

KlausST said:

Hi,

it depends on the device you are using.

For usual logic ICs (HC, HCT...) you must not give HIGH signal to an unpowered device. --> read the datasheet
But other families like AHC, AHCT will can widthstand HIGH signal when not powered. --> Read the datasheet. (also about output signal when not powered)

Klaus

Click to expand...

Thanks klausst.
But i still have doubt. The question is basic inverter analysis.
When the Vdd is off and we apply input the inveter, the output is X. But how it goes to X.
Can anybody explain??

Hi,

In most cases: you must not apply a signal to the input if an unpowered device. Else you risk damage of the device.
Thus the answer can't be global.

If you have a specific device in mind: either you or we need to read the datasheet.
If you wang us to verify your statements, then upload the datasheet.

X = don't care. It's either HIGH or LOW

Klaus

CMOS inverter is quite basic, why don't you simulate it? You will get an exact transfer characteristic for any X input value. It should explain a lot.

IngleA said:

Thanks klausst.
But i still have doubt. The question is basic inverter analysis.
When the Vdd is off and we apply input the inveter, the output is X. But how it goes to X.
Can anybody explain??

Click to expand...

Please remember that X has no physical meaning, it's a simulation trick we do, typically for digital design.

IngleA said:

Hi all,

I have two questions regarding CMOS inverter output.

1) When the Vdd is off and my input to inverter is still present (0 or 1). what is the output.
I think it gives X, but dont know how.


2) When Vdd is applied but my input is X. In this scenario what is the output?

Please help. would appreciate.

Thanks

Click to expand...

1) Remember that VDD is required to charge or discharge the output load capacitance. Also remember that X in silicon is an unknown value. Keeping these 2 things in mind, when Vdd is off, then output of load capacitance is unknown. In most cases, by design intent we do not care about the output. There should be some clamp value at interface of this power domain when it is turned down to keep it functionally correct.

2) Same thing here, output will be X (an unknown) from simulation perspective. From silicon perspective, there will be certain value (unknown) at input that can charge or discharge this load capacitance. This might result in functional failure in downstream logic.

When a power domain of logics are turned, all its outputs become "unknown". For an inverter, it can switch to LOW when there is a HIGH input. But the reverse cannot be said when its input is driven with a LOW (it will enter into metastable state). This is why outputs of power-gated domains usually has an isolation cell that will "remember" its signal before the power domain is turned off.

Most CMOS gates have input protection diodes which will
shunt input current into VDD from any "high" input. This can
provide the internal bias for a relatively strong "0" at the
output.

-All- inputs at zero should leave the output high-Z (weak
and undefined. But any one (or more) input high can power
up the guts.