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[SOLVED] I can't find the transistors in the layout in Encounter and Virtuoso

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michael_mikhael

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I wrote a verilog code, then I synthesized it in Encounter RTL compiler and imported the design in Encounter, I was trying after that to import it to Virtuoso as a DEF or GDS, the problem is that I can only seen the metals and vias in both Encounter and Virtuoso but not the transistors. I followed the the steps in many tutorials and I'm still wasn't able to fix this issue.

.jpg

Screenshot-15.png
 

Have you ever tried to increase View Level/Depth to max. ?
 

that didn't work and I'm getting this:

The referenced cell "or2_1" was not found. The OpenAccess design data was created for this cell without any reference. Ensure that the referenced cell exists and the Lib is defined in library definition file.
 

michael_mikhael said:
that didn't work and I'm getting this:

The referenced cell "or2_1" was not found. The OpenAccess design data was created for this cell without any reference. Ensure that the referenced cell exists and the Lib is defined in library definition file.
Click to expand...

Your virtuoso environment is not set correctly. It doesn't know where to look for the layout of the individual cells.

You can export a GDS from encounter that has all cell info in it, or fix your virtuoso library.
 
Hi, guys its, me again. I'm still tryning to run a verilog code that I wrote its an OR gate, nothing complicated, when I synthesized it to use it in virtouoso, I wasn't able to find the transistors, what I did was write a code in verilog, synthesize it in Encounter and saving it as GDS2 3to import it to virtuoso, and in virtuoso I wasn't able to se the transisgtors, and the I'm getting the error that I got I mentioned befrore "The referenced cell "or2_1" was not found. The OpenAccess design data was created for this cell without any reference. Ensure that the referenced cell exists and the Lib is defined in library definition file." and I still haven't figured out how to fix it
 

michael_mikhael said:
Hi, guys its, me again. I'm still tryning to run a verilog code that I wrote its an OR gate, nothing complicated, when I synthesized it to use it in virtouoso, I wasn't able to find the transistors, what I did was write a code in verilog, synthesize it in Encounter and saving it as GDS2 3to import it to virtuoso, and in virtuoso I wasn't able to se the transisgtors, and the I'm getting the error that I got I mentioned befrore "The referenced cell "or2_1" was not found. The OpenAccess design data was created for this cell without any reference. Ensure that the referenced cell exists and the Lib is defined in library definition file." and I still haven't figured out how to fix it
Click to expand...

read my comment again. you can fix this in encounter (during export) or in virtuoso. the tools cannot guess where the cells are, you have to give the tools a reference. this is well covered in tutorials for both encounter and virtuoso.
 

When I export the gds in Encounter I add the Virginia tech stream out map, and in Virtuoso I use the .gds file exported from Encounter and I use the viginia tech stream in map, so I'm not sure what else I'm missing
 

michael_mikhael said:
When I export the gds in Encounter I add the Virginia tech stream out map, and in Virtuoso I use the .gds file exported from Encounter and I use the viginia tech stream in map, so I'm not sure what else I'm missing
Click to expand...

your reading comprehension is mighty low. read my comment again, please. did I mention a stream map was lacking? No, I did not. I said the cells are lacking. Have you searched how to add a cell library at export time in encounter? I refuse to spoon-feed this to you, it's so simple.
 

"your reading comprehension is mighty low.", lol, I think so. I'm gonna try something out and let you know how it goes, thanks
 

Its me again, I got the layout to work but now I have problems with the schematic, I import the synthesized Verilog code to the same library I'm using for the layout but the simulation is not working, I'm using Specter for the simulation, when I descend in the hierarchy in the schematic I don't find the transistors.Screenshot-18.pngScreenshot-19.pngScreenshot-20.png
 

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