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PVS LVS error details

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NikosTS

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Hello everyone,
I am using Cadence PVS for the first time for LVS and DRC. In DRC the error fixing is straightforward as I can zoom in to the errors and fix them.
In the LVS though, i can't find many details on how to fix an error if such occurs. For example, i was doing the simplest layout of an Inverter. I connected everything except for the gates of the NMOS and PMOS on purpose. The tool produced an error of "unmatched instances" but no further details. In Assura that I am generally using, there are options to show more details and in the above mentioned example there would be a "net error" that would say that "netX and netY" should connect together.
In such a trivial layout it is easy to spot the problem , but when it comes to large layouts the details are needed to solve the problems.
Is there a way to show more details like in Assura?

Thank you in advance
 

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