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[SOLVED] Comparing ASIC gate-equivalent with Xilinx FPGA LUTs

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dpaul

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Hi,

We all know that the synth report contains a table that contains the number of resources utilized. I am particularly interested in the number of LUTs utilization counts (lets us ignore the BUF*, MMCM/PLL, DSP-slices, BRAMs, etc). Now there are stuff like LUT1, LUT2, LUT3, LUT4, LUT5 and LUT6. The synth report will contain the amount utilized by each of these LUTs.

Now lets assume that someone asks me if I can find out how many LUTs will be utilized if I want to implement a 100,000 gate ASIC in a Ultrascale or a 7 series Xilinx FPGA.
How do I find that? How can I *roughly* map the gate equivalent count to the LUTs count? Any suggestions?


I have referred to this 2015 blog from Synopsys and there is a reference to Xilinx in it:
https://blogs.synopsys.com/breaking...many-asic-gates-does-it-take-to-fill-an-fpga/

It says, 1* LUT = 6 Two input NAND Gate equivalent (go try it!)

What I don't understand is what is exactly meant by "LUT". Because in Xilinx devices we have LUT1, LUT2, LUT3, LUT4, LUT5 and LUT6. Is it indicating that I combine all the LUT* counts from my synth report and use that value in comparing with the gate equivalent count?

Any ideas?
 

Given the blog post is on Virtex-5,6,7, and Ultrascale a LUT is a 6-input Look Up Table. i.e. a memory with 6 address lines.
The Xilinx designation of LUT1, ..., LUT6 is for various LUT configurations with 1 through 6 inputs used.
 

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It is hard to find equivolent.
The more modern devices have LUT6s, ie. all LUTs have 6 inputs.
But, all that means is each lut can have anywhere from 1 (for a simple inverter) to 6 inputs (for a multi-gate LUT). So what might be 10 gates in an asic might fit in a single LUT in the FPGA or it might take 10. It depends on the function. Because of this gate equivolence is pretty meaningless. It all depends on function. For two separate 100k gate ASICs, one might fit in a given FPGA and the other wont.

(This also doesnt take into account LUT packing, which is where the synthesis might decide it can pack two separate parts of your RTL into a single LUT)

When Xilinx reports LUT2/3/4 etc, thats just the number of inputs used in a given LUT6 on the fabric.

To be fair, Synopsis have much more experience at this than most, so using their formula is probably about as good as a rough estimate can be.
Be aware though, that blog post is 3 years old, and Ultrascale is now available with new technology!
 

    V

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It is explicit in some documents (for example, ug384, figure 6) that LUT6 = 2 x LUT5.

I assume the same correlation is valid for other LUT.
 

It is explicit in some documents (for example, ug384, figure 6) that LUT6 = 2 x LUT5.

I assume the same correlation is valid for other LUT.

No, you can't get LUT6 = 6 LUT1's or LUT6 = 3 LUT2...

The only reason for the LUT6 = 2xLUT5 is there are two outputs on a LUT structure. This was expressly done to improve LUT packing as it makes a lot less sense for packing if you have a 6-input LUT serving as only an inverter. Having a 4-input LUT serving as an inverter isn't very efficient but it's 4x less logic than the 6-input LUT as an inverter.

Older families of Xilinx parts (with 4-input LUTs, Pre V5) didn't have two outputs. Altera has had a structure that allows allocation of their LUT structure to give you various combinations of inputs for each of their two LUT outputs (they've had this since very early Statix parts. Because of this feature, Altera packing can be more efficient than Xilinx LUT packing.
 

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