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NC verilog schematic to verilog

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jiminization

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I am using the Virtuoso NC-Verilog to convert my schematic to a verilog netlist. However, some of my instance name were renamed.
It uses the prefix "Inst_" instead of the name in the schematic. This causes some errors when I apply the sdf in this netlist.
How can I retain the name in the schematic? Thank you
 

jiminization said:
I am using the Virtuoso NC-Verilog to convert my schematic to a verilog netlist. However, some of my instance name were renamed.
It uses the prefix "Inst_" instead of the name in the schematic. This causes some errors when I apply the sdf in this netlist.
How can I retain the name in the schematic? Thank you
Click to expand...

You can always rely on an external tool to do a search and replace, perhaps with regex even.
 

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