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Is it possible to fetch data from DDR3 and feed it to JESD204B?

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msdarvishi

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Dear all,


I am working with Vivado 2017.3 targeting a KC705 FPGA.


I have a design including a Microblaze, an AXI_PCIe, and a MIG 7SEries DDR3 memory. Both Microblaze and DDR3 can read/write data from/to DDR3 and it works very well.


Now, I have added a JESD204 module and implemented my design. I am wondering whether there is a way to fetch data already written in DDR3 from this module and put it at the head of JESD204 (feeding it to the JESD204 module).


Is it possible or a way to do it? I was thinking to AXI_DMA but I am not sure where it is the solution or not.


Any help and guide are in advance appreciated.


Bests,
 

Of course there're ways...
The MIG7 (DDR3) uses either a native interface or an AXI parallel bus while the JESD204 is a serial high speed protocol.
If I had to design something custom I'd read the data from the DDR - store it in a FIFO and have the output of this FIFO to feed the channel towards your DAC/ADC. This will also require adding the AXI stream control signals for the JESD204...
This essentially converts the memory mapped interface with the DDR to a streaming interface.

Xilinx has IPs such as the DMA and AXI Stream to MM and Stream to MM converters that can simplify your job...
But Stream to MM and MM to Stream conversions are very common in FPGA designs. So perhaps you want to try and implement it by yourself using pure HDL - just for the purpose of learning.
 

Of course there're ways...
The MIG7 (DDR3) uses either a native interface or an AXI parallel bus while the JESD204 is a serial high speed protocol.
If I had to design something custom I'd read the data from the DDR - store it in a FIFO and have the output of this FIFO to feed the channel towards your DAC/ADC. This will also require adding the AXI stream control signals for the JESD204...
This essentially converts the memory mapped interface with the DDR to a streaming interface.

Xilinx has IPs such as the DMA and AXI Stream to MM and Stream to MM converters that can simplify your job...
But Stream to MM and MM to Stream conversions are very common in FPGA designs. So perhaps you want to try and implement it by yourself using pure HDL - just for the purpose of learning.


Hi Shaiko,

Thanks for your reply and explanation. I did nit get your point. So, if it is possible, how can I do it? Should I change the MIG configuration, or add a FIFO, use AXI DMA, or etc? Your explanation is very nice but a little bit vague to me. Can you please elaborate more on that?

Thanks,
 

My answer will focus on a custom HDL solution that involves reading data from DDR3 and sending it towards the DAC:

1. I assume that you have the interface towards the DDR3 memory controller and DAC/ADC tested and working.
2. The interface towards the memory controller for the 7 series FPGAs can be either native or AXI. But it doens't really matter as both are memory mapped - I.E: when you want to read data, you apply the address (from the location you want to read) in coherence with the required control signals according to the interface you use.
3. Efficient transactions with DRAM (your DDR3) always involves addressing large chunks of spatially adjacent data - so keep the random accesses to the absolute possible minimum - I won't get into why this makes things more efficient (you can google about it) - just accept it as a fact.
4. The data bus from the memory controller is wide - maybe 128 bits or a higher power of 2. Connect this bus to a write port of a FIFO.
5. Shortly after a read transaction from the memory controller is initiated - data will be fetched and written to this FIFO.
6. The read port of the FIFO will be the data source of your interface to the JESD204 which as you probably know is a streaming interface - I.E: data, valid and perhaps end of packet notification.
7. Once enough data for one or more packets are fetched from the DDR3 and written to the FIFO from - you can initiate a transaction towards the DAC over the JESD204 can be initiated.
8. The AXI Stream "valid" signal is the "read" from the FIFO.
 

My answer will focus on a custom HDL solution that involves reading data from DDR3 and sending it towards the DAC:

1. I assume that you have the interface towards the DDR3 memory controller and DAC/ADC tested and working.
2. The interface towards the memory controller for the 7 series FPGAs can be either native or AXI. But it doens't really matter as both are memory mapped - I.E: when you want to read data, you apply the address (from the location you want to read) in coherence with the required control signals according to the interface you use.
3. Efficient transactions with DRAM (your DDR3) always involves addressing large chunks of spatially adjacent data - so keep the random accesses to the absolute possible minimum - I won't get into why this makes things more efficient (you can google about it) - just accept it as a fact.
4. The data bus from the memory controller is wide - maybe 128 bits or a higher power of 2. Connect this bus to a write port of a FIFO.
5. Shortly after a read transaction from the memory controller is initiated - data will be fetched and written to this FIFO.
6. The read port of the FIFO will be the data source of your interface to the JESD204 which as you probably know is a streaming interface - I.E: data, valid and perhaps end of packet notification.
7. Once enough data for one or more packets are fetched from the DDR3 and written to the FIFO from - you can initiate a transaction towards the DAC over the JESD204 can be initiated.
8. The AXI Stream "valid" signal is the "read" from the FIFO.


Hi @Shaiko,

Thanks for you good explanation. Just as a question, by this implementation, where would be the location for DMA IP and how should I connect it in my design?

Bests,
 

My answer will focus on a custom HDL solution that involves reading data from DDR3 and sending it towards the DAC:

1. I assume that you have the interface towards the DDR3 memory controller and DAC/ADC tested and working.
2. The interface towards the memory controller for the 7 series FPGAs can be either native or AXI. But it doens't really matter as both are memory mapped - I.E: when you want to read data, you apply the address (from the location you want to read) in coherence with the required control signals according to the interface you use.
3. Efficient transactions with DRAM (your DDR3) always involves addressing large chunks of spatially adjacent data - so keep the random accesses to the absolute possible minimum - I won't get into why this makes things more efficient (you can google about it) - just accept it as a fact.
4. The data bus from the memory controller is wide - maybe 128 bits or a higher power of 2. Connect this bus to a write port of a FIFO.
5. Shortly after a read transaction from the memory controller is initiated - data will be fetched and written to this FIFO.
6. The read port of the FIFO will be the data source of your interface to the JESD204 which as you probably know is a streaming interface - I.E: data, valid and perhaps end of packet notification.
7. Once enough data for one or more packets are fetched from the DDR3 and written to the FIFO from - you can initiate a transaction towards the DAC over the JESD204 can be initiated.
8. The AXI Stream "valid" signal is the "read" from the FIFO.


Hi,

For the simplicity, I put a snapshot of my block design based on your advice.

Now, Can anyone let me know am I missing something?? How can I create the link between DDR3, FIFO and JEAD204? Please note that the S_AXI port of the axi_periph_interconnect in this diagram is connected to the Microblaze.

Screenshot from 2018-09-28 17-18-16.png
 

Hi,

For the simplicity, I put a snapshot of my block design based on your advice.

Now, Can anyone let me know am I missing something?? How can I create the link between DDR3, FIFO and JEAD204? Please note that the S_AXI port of the axi_periph_interconnect in this diagram is connected to the Microblaze.

View attachment 149294


Any help or advice here?
 

You have to write your own HDL design to do that.
Making a FPGA is generally more complicated than putting a blocks and connecting it with mouse clicks.
 

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