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Hysteretic Comparator with internal positive feedback

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tenso

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hyscomp.PNG

I am attaching the schematic from Allen/Holberg of a comparator with hysteresis using internal positive feedback

I was hoping someone here could answer some of my questions.

1) How do the cross-coupled PMOS current mirrors enforce positive feedback?

2) The book says that there is both negative and positive feedback in the circuit above and that the +ve feedback factor ( and I think by extension loop gain) should be greater than the negative feedback factor to give hysteresis. The book says that there is current-series feedback ( I think this means series-series feedback?) through the common source node of M1 and M2, and that this is negative. The second is voltage shunt feedback ( I think this means shunt shunt feedback?) through the gate drain node of M6 and M7.
Can someone help me recognize the negative and positive feedback loops and the types of feedback for each loop?


Also if someone can link to the paper where the above architecture was proposed, that would be helpful.
Thanks
 

Cross-biased mosfets are seen in the RS flip-flop. A certain amount of hysteresis is built in, since your schematic does not have abrupt switching but gradual.
 

Depending on the relative weighting of the mirrors
(mirror gain, M6/M3 and M2/M4) you can have either
linear gain or some hysteresis.
 

I can't help you to identify the feedback loops, but maybe it helps a bit.
Imagine the circuit without M6,7. The gain is Au=gm1,2/gm3,4, simple diff.pair with diode loads. Diode connected transistor is a negative feedback to reduce its output resistance for example.
If you add M6&M7 the gain will increase with the added transistors, because they add positive feedback to the circuit, or negative resistance in parallel with the diodes: Au=gm1,2/(gm3,4-gm6,7). I think yes, this is a shunt-shunt feedback.
If gm6,7=gm3,4 (so the sizes of the diodes and cross-coupled devices are the same) you can see the gain is infinite. And if gm6,7>gm3,4 that creates the hysteresis.
The hysteresis depends on the gm, so not just on the device ratios, with extra tail current you can increase it.
 

I can't help you to identify the feedback loops, but maybe it helps a bit.
Imagine the circuit without M6,7. The gain is Au=gm1,2/gm3,4, simple diff.pair with diode loads. Diode connected transistor is a negative feedback to reduce its output resistance for example.
If you add M6&M7 the gain will increase with the added transistors, because they add positive feedback to the circuit, or negative resistance in parallel with the diodes: Au=gm1,2/(gm3,4-gm6,7). I think yes, this is a shunt-shunt feedback.
If gm6,7=gm3,4 (so the sizes of the diodes and cross-coupled devices are the same) you can see the gain is infinite. And if gm6,7>gm3,4 that creates the hysteresis.
The hysteresis depends on the gm, so not just on the device ratios, with extra tail current you can increase it.

Thanks for taking the time to answer. Your post helped. If I am not mistaken the widths of M6 and M7 ( the cross coupled transistors ) is usually made larger and as you said you can decided the trip points of the hysteretic comparator using the tail current and the betas of the transistors.

I had a follow up question. Baker's book had the following schematic with a separate pre-amplifier and the positive feedback hysteretic part. I was wondering if they are any pros, cons to this architecture as opposed to the one in the OP. From your gain equations it seems that the circuit in OP would have higher DC gain and also minimize power consumption.

baker_comp.PNG

- - - Updated - - -

Depending on the relative weighting of the mirrors
(mirror gain, M6/M3 and M2/M4) you can have either
linear gain or some hysteresis.

right, I think if you have wider widths for the M6 and M7 transistors you can create a hysteresis.
 

It has a benefit that if the input stage is separated, the kick-back effect of the output stages at transitions will be less. So the comparator can be controlled with higher source resistances. Otherwise I don't know, I think the offset is higher with low gain input stage and the speed is not improved with 3 stages. I don't get it how the last stage's tail current is controlled actually. Baker should explain it.
 

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