Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

High Frequency Resistor Modeling

Status
Not open for further replies.

Puppet123

Full Member level 6
Joined
Apr 26, 2017
Messages
356
Helped
22
Reputation
44
Reaction score
21
Trophy points
18
Activity points
3,059
Hello,

I am attempting to model a resistor for use in a high frequency design (over 50GHz) in Bipolar.

Can I "EM Simulate" this or should I just do Z parameter extraction in a simulator to get a T model for the structure.

I want to make sure it is not adding capacitance to my design and I am not sure I fully trust the PDK over 50GHz.

What can I do ?

Thank you.
 

I would trust the PDK Model more than EM, because the EM stackup between Poly layer and substrate might not be accurate enough. Or at least check it against capacitance to substrate from the process spec.

Often, the EM stackup is designed for simulation of the "upper" metal layers and simplified down at the Poly layer. If you use it, check it carefully.
 

You should give some thought to which parasitic capacitances
should be put inside the RF macromodel, and which should be
left to the higher level netlist. This means understanding the
big-picture extraction scheme and the "to where?" for the
capacitances that resistor PCell layout features creates. You
don't want to be double-counting endcap C or neglect it,
either. May need to do a couple of adjunct EM simulations,
like one without the resistor body but including sensible
interconnect, and one with just the resistor body. And
what about over-routes? What will you assume? What will
the higher level layout extraction do?
 

Dick_FreeBird,

Thanks.

RC Extraction, it is my understanding, won't capture require parasitic inductive effects after about 35 GHz, so then it would be necessary for me to do EM simulation then on the interconnect connecting the resistors and also the vias/interconnect of the resistor - but not the body of the resistor.

I think making the EM simulations of the interconnect scalable would be a good approach then I can just add interconnect when I need it and see the effects.

One example of a potential problem area would be in Bipolar, especially at the emitter of the transistor I would have to make sure there was sufficient modeling of the capacitance there, as it could cause oscillation with capacitance at the emitter reflected back to the base.

Does this approach make sense ?

Thank you.
 

I would trust the PDK Model more than EM, because the EM stackup between Poly layer and substrate might not be accurate enough. Or at least check it against capacitance to substrate from the process spec.

Often, the EM stackup is designed for simulation of the "upper" metal layers and simplified down at the Poly layer. If you use it, check it carefully.

Should I do a Parasitic Extraction of it instead ?
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top