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How do I design a schematic for Counter with Reset/Pause on FPGA?

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How do i design a schematic for Counter with Reset/Pause on FPGA

Hey All!


Currently struggling a tonne getting my mind around designing basic schematics on an FPGA (Device is a Cyclone IV E EP4CE6E228). Basically the schematic is supposed to make a digit move across 3 of the 4 7-segment displays (with an indicator of direction on the 4th). Out of the 4 buttons avaible 1 needs to be a Reset/1 needs to be a Pause and the remaining 2 for selecting Frequency. I'm honestly really lost at the moment, and can't seem to find much information on making these Schematics (Most tutorials are VHDL coding). I'm using Quartus for this!

An example High Level Design is attached for reference.
I think i've figured out the Freq. Divider, Freq. Selector, Selection MUX and 7 Segment Decoder.

HLD.PNG
 

Re: How do i design a schematic for Counter with Reset/Pause on FPGA

Start from drawing your design and every component on the paper. You don't need to know VHDL to do so.
Then draw the design in the schematic and simulate the design.
With which part of the schematic you have a problem right now?
 

Re: How do i design a schematic for Counter with Reset/Pause on FPGA

Hi

15377390315181980784287.jpg

See attached photo. I hope this is what you were asking for. I just made that up though and I believe it would do. I noticed that you don't have a button for direction, or perhaps you want to do that with some internal logic? The appropriate logic signals to the control inputs of the tristate buffers should implement the shifting with clock. Connecting your pause button to the ENABLE input of all registers should implement the pause function.

Should you need more clarification, let us know. We could give more help.
 

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