T
treez
Guest
Hello,
We have a D2PAK FET in a linear LED driver. It dissipates some 13W. It sits on a thermal pad which lies on a big metal heatsink.
We have got our PCB done with multiple epoxy filled thermal vias in the pad of the D2PAK...in fact, its a “Lattice” of 0.5mm diameter thermal vias whose centres are 0.9mm apart...so in fact, there are 140 thermal vias in the drain pad of the D2PAK. This lattice of thermal vias is to be entirely plated over with copper...(copper actually over the via openings).
Do you think we have got the thermal vias too close together? (There is only 0.4mm between the via hole perimeters)
We have a D2PAK FET in a linear LED driver. It dissipates some 13W. It sits on a thermal pad which lies on a big metal heatsink.
We have got our PCB done with multiple epoxy filled thermal vias in the pad of the D2PAK...in fact, its a “Lattice” of 0.5mm diameter thermal vias whose centres are 0.9mm apart...so in fact, there are 140 thermal vias in the drain pad of the D2PAK. This lattice of thermal vias is to be entirely plated over with copper...(copper actually over the via openings).
Do you think we have got the thermal vias too close together? (There is only 0.4mm between the via hole perimeters)