Asynchronous assertion and synchronous deassertion of reset

Hello everyone!

I have no ASIC experience, but FPGA one only. I have one question regarding ASIC. Let's say I have a negative-active reset with asynchronous assertion and synchronous deassertion. As I understand it's totally safe to connect this reset to a FF's synchronous reset input. Do you agree? My arguments:
1). Asynchronous assertion is not a problem for both asynchronous and synchronous inputs, because the reset has a long duration.
2). Even if a clock is not active during the whole reset, such a FF will be reset anyway, because the presence of the clock in the end of the reset sequence for synchronous deassertion guarantees at least several clocks (corresponding to a number of FFs in the reset synchronizer) of synchronous-like reset pulse (0 was set long time ago and it's sampled synchronously at the fist clock appeared and then/ a few cycles LATER, 1 is sampled synchronously).

Regardless of how long the asynchronous assertion lasts, once that is removed the de-assertion time is determined by the number of FFs in the synchronizer. That could be as short as one clock cycle, but that should be enough for your synchronous resets to capture it. Draw a timing diagram.

A reset synchronizer needs two FFs, not more, not less. There should be individual synchronizers for each clock domain.


I agree with the initial considerations, if you don't worry about possible metastable events during reset assertion.