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Large FPGA with logic only

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sythe

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I need a large FPGA with as mush as possible LE/CLB only (or near to).
The reason is that I need to emulate our ASIC design on it.
The design does not make use of any particular interface like SerDes, PCIE etc etc.

Any one an idea which device to select ?

br,

Simon
 

Until the V series Altera (now Intel) - used to have the E family of devices (for example Stratix V E) which had mostly logic without high speed interfaces.
But the newest FPGAs from Intel and Xilinx always have additional interfaces.

But why do you care? Just don't use them...

P.S:
If your ASIC is large it may not fit into a single FPGA and will require careful partitioning between more than one device.
For that purpose ASIC prototyping solutions exist. For example - the Synopsys HAPS:

https://www.google.co.il/search?q=S...4sKHaf-D1QQ_AUIDigB&biw=1704&bih=948&dpr=1.13

These may cost an order of magnitude more than a simple evaluation board - but may be worth it for large complex designs.

Good luck.
 
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    sythe

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Thanks for the comment.

We have our own custom HAPS ;)

We created a specific carrier board which can hold an COTS FPGA, which will be used as stimuli block, and a custom add-on board with socket, which will contain a device under test.
For the last we would like to have a drop in replacement, that has an FPGA, so that we can do early proof of concepts for future generation products.
Since our design is not really huge, it will still fit in a big FPGA.

br,

Simon
 

For the last we would like to have a drop in replacement
Click to expand...
If I where to design that system - I'd make sure that the interconnect between boards is done via an FMC or an FMC+ connector.
This way the drop - in board wouldn't have to be custom designed (as most COTS evaluation / development boards today use this type of connector).

Less (or better yet non at all) custom board design is usually the north star...
 

I need a large FPGA with as mush as possible LE/CLB only (or near to).
The reason is that I need to emulate our ASIC design on it.
Click to expand...

Without 2nd thoughts, for Xilinx it would be the Ultrascale series.
 

A word of caution.

Some of largest FPGAs from Xilinx use a non monolithic die. This can bring challenges in routing if a large logical block is partitioned between slices.
I've had this problem with Virtex 7 - and had to opt for major changes in the RTL just to make it route successfuly.
The same design (prior to the changes) worked without any issues on a Static V
 

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