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High speed driver for driving a large number of lines simultaneously

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little0192

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High speed driver for driving large number of lines simultaneously

Hi,
I am working on a mux board design. I am using an 8:1 mux with 3 selection lines and digital pin input Capacitance of 2pF(typical). The total number of mux ic is 256. Which is controlled by the FPGA pin having drive strength of the 8mA max at 2.5V. The max propogation delay should not exceed 12ns.

I am confused which circuit will be best suitable as a driver between the FPGA and the 256 Mux select lines. Is a BJT Darlington pair will be better than this?

So far I have simulated a driver using an opamp as a comparator. (LTC6752) but not getting the desired results. I am attaching the snapshots of the simulations.

MUX IC details :
DIGITAL INPUTS
Input High Voltage, VINH 1.7 V min
Input Low Voltage, VINL 0.7 V max
Input Current
IINL or IINH 0.005 µA typ VIN = VINYL or VINH
±0.1 µA max
CIN, Digital Input Capacitance 2 pF typ

Capture.JPG

the above simulation was done assuming 4pF total capacitance per pin and driving single pin for 128 ICs = 4pF*128= 512pF
The input signal is a 40Mhz clock signal with 10ns rise/fall time.
The max current through the load capacitor is 30ma which is higher than the opamp max output current of +-20mA.

current.JPG
 

Re: High speed driver for driving large number of lines simultaneously

Why would you use an opamp for a digital circuit? And Darlingtons tend to be slow. Why don't you use a DIGITAL device in your DIGITAL circuit??

There are lots and lots of drivers/buffers out there. You may want to use several drivers rather than trying to drive all 256 lines with a single driver. Your selection will depend on available voltages, etc. For starters, look at something like a 74LV244.

Also, you've got a signal with 10nS rise time, but you want a maximum of 12nS propagation delay? That might be a problem.
 
Re: High speed driver for driving large number of lines simultaneously

Hi,

Yes, Opamp is not suitable.

The fastest is if the signals are generated by the FPGA as multiple outputs.
Now if you want to drive 256 then these are a lot of lines....

If you want to reduce lines, then my first approach is to use the squareroot method:
sqrt(256) = 16.
This means 16 groups with 16 devices (MUX) each.

Now the solution could be: 1 group (x3 lines) from FPGA --> 16 (x3) buffers --> to 16 MUXes each
or 16 groups (x3) from FPGA --> to 16 MUXes each

There are numerous solutions.
What´s the best depends on:
* how many signal lines are available at the FPGA (usually they come with many IOs)
* drive strength of FPGA
* drive strength of drivers
* delay of drivers

Excel could help you to find the best solution.

Klaus
 
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