little0192
Newbie level 6
High speed driver for driving large number of lines simultaneously
Hi,
I am working on a mux board design. I am using an 8:1 mux with 3 selection lines and digital pin input Capacitance of 2pF(typical). The total number of mux ic is 256. Which is controlled by the FPGA pin having drive strength of the 8mA max at 2.5V. The max propogation delay should not exceed 12ns.
I am confused which circuit will be best suitable as a driver between the FPGA and the 256 Mux select lines. Is a BJT Darlington pair will be better than this?
So far I have simulated a driver using an opamp as a comparator. (LTC6752) but not getting the desired results. I am attaching the snapshots of the simulations.
MUX IC details :
DIGITAL INPUTS
Input High Voltage, VINH 1.7 V min
Input Low Voltage, VINL 0.7 V max
Input Current
IINL or IINH 0.005 µA typ VIN = VINYL or VINH
±0.1 µA max
CIN, Digital Input Capacitance 2 pF typ
the above simulation was done assuming 4pF total capacitance per pin and driving single pin for 128 ICs = 4pF*128= 512pF
The input signal is a 40Mhz clock signal with 10ns rise/fall time.
The max current through the load capacitor is 30ma which is higher than the opamp max output current of +-20mA.
Hi,
I am working on a mux board design. I am using an 8:1 mux with 3 selection lines and digital pin input Capacitance of 2pF(typical). The total number of mux ic is 256. Which is controlled by the FPGA pin having drive strength of the 8mA max at 2.5V. The max propogation delay should not exceed 12ns.
I am confused which circuit will be best suitable as a driver between the FPGA and the 256 Mux select lines. Is a BJT Darlington pair will be better than this?
So far I have simulated a driver using an opamp as a comparator. (LTC6752) but not getting the desired results. I am attaching the snapshots of the simulations.
MUX IC details :
DIGITAL INPUTS
Input High Voltage, VINH 1.7 V min
Input Low Voltage, VINL 0.7 V max
Input Current
IINL or IINH 0.005 µA typ VIN = VINYL or VINH
±0.1 µA max
CIN, Digital Input Capacitance 2 pF typ
the above simulation was done assuming 4pF total capacitance per pin and driving single pin for 128 ICs = 4pF*128= 512pF
The input signal is a 40Mhz clock signal with 10ns rise/fall time.
The max current through the load capacitor is 30ma which is higher than the opamp max output current of +-20mA.