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Dummy Metal Fill Issues in MMWave IC Layout in Bi(CMOS)

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Puppet123

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Hello,

I am doing MMWave IC Layout in (Bi)CMOS processes and am wondering about the effect of metal fill on my passives and interconnect.

Should I EM or schematically simulate the passives and interconnect with a non dummy metal fill and then re simulate again with the dummy metal fill ?

How would I handle this in my design flow - since some or all of the layers in metal fill are automated by the foundry or the PDK.

Thank you.
 

My thought:

There may be impact on dummy fill on interconnect in spice extraction as it depends on which technology you are in. For older node technologies I do not think there would be any impact on having dummy metal fills in design or it can be minimal. However in case of latest technology nodes, there is impact on having dummy fills near to critical nets.
Also in case extraction deck consider dummy fills, then there is point on the running the design with having dummy metal fill shapes to see if . In case extraction runset does not consider the dummy fill then there is no point in running the design with having fill shapes.

On EM, I do not think there would be any impact on dummy fill as EM is current density flowing through metal shape.
 

npardeepsain said:
On EM, I do not think there would be any impact on dummy fill as EM is current density flowing through metal shape.
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If you look at high Q inductors and forget to block dummy metal fill inside the inductors, this can decrease Q factor. I showed that effect here: https://muehlhaus.com/support/rfic-em-appnotes/60-ghz-balun-filler-effect

Including dummy metal fill in EM simulation can create excessive modell size, depending on the EM method used. I would recommend FDTD for this task.
 

Hello Volker@muehlhaus,

Thank you for your email.

Typically in your IC design flow, do you design and simulate your passives taking into account the metal fill (over designing by 10% and then adding the metall fill before you tape out) or should you literally add the metall fill when characterizing the inductors as part of the design flow.

Thank you.
 

For SiGe that I work with most, EM simulation is almost always done WITHOUT dummy metal fill, and metal fill is blocked in the inductor area on all layers. So we usually do NOT simulate it. The investigation of metal fill using EM in my link was just to double check how large the effect is.

Your technologies's design rules might be different, so check if you are allowed to block fillers there.
 
Hello Volker@muehlhaus,

Thank you for your email.

So then over design your passives to compensate for eventual metal fill later in the the design process ?

Thank you.
 

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