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I want to design my own processor as hobby for learning purpose, where to start

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matrixofdynamism

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I want to learn how a processor design is carried out and design my own in VHDL and implement it on FPGA. What book should I use to get started?
The data bus shall be 16 bit. The program memory shall be separate from the data memory. I only require addition and subtraction operations. The processor must be simple, nothing fancy is required. It should require minimum amount of logic resources.
 
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matrixofdynamism said:
I want to learn how a processor design is carried out and design my own in VHDL and implement it on FPGA. What book should I use to get started?
Click to expand...

Look for David Patterson's work on RISC. That should give you a good starting point.
 

why not write an emulator of your CPU first (in C or another language)? That way, you will have a reference model to test against?
 

In school we did this project with an external ALU and external memory (the memory held the microcode too if I recall correctly) with the CPLD implementing the control logic between all of them.

Having that external ALU was a good constraint and starting point for such an introductory project. Even if you do it all in an FPGA do break it into these separate pieces.

Perhaps you can find a college website with a similar CPU project and follow from that.
 

Start by realizing that anything bigger than an 8-bit uC
is beyond an individual's efforts, let alone an individual
poking at it in their spare time. Bigger chips are team
efforts, because.

Then pick an architecture and maybe an example with
good literature, and attack the blocks and top level.

Old AMD bit-slice chips could be an interesting waypoint.
The 2900 series had a lot of functions (my first job out
of school was replicating several of them; and we had a
small team to get them all done (enough to make a
MIL-1750 flight computer) in a couple of years). You
could get a hardware stab done with PCB design and
the chip set (if they are still available, or newer
incarnations) and then work on porting that, now
proven (if) to a single chip implementation - might
even find IP blocks corresponding, so you could spend
time on architecture and optimization rather than
(say) being the umpty-umpth guy coding up the same
microprogram control unit.
 

dick_freebird said:
Start by realizing that anything bigger than an 8-bit uC
is beyond an individual's efforts, let alone an individual
poking at it in their spare time. Bigger chips are team
efforts, because.

Then pick an architecture and maybe an example with
good literature, and attack the blocks and top level.

Old AMD bit-slice chips could be an interesting waypoint.
The 2900 series had a lot of functions (my first job out
of school was replicating several of them; and we had a
small team to get them all done (enough to make a
MIL-1750 flight computer) in a couple of years). You
could get a hardware stab done with PCB design and
the chip set (if they are still available, or newer
incarnations) and then work on porting that, now
proven (if) to a single chip implementation - might
even find IP blocks corresponding, so you could spend
time on architecture and optimization rather than
(say) being the umpty-umpth guy coding up the same
microprogram control unit.
Click to expand...

I beg to difer:

https://github.com/darklife/darkriscv

A RISC-V implemented in one night: "Developed in a magic night of 19 Aug, 2018 between 2am and 8am, the darkriscv is a very experimental implementation of the opensource RISC-V instruction set"

There are some nice implementations with few lines of code, as J1 processor:

https://www.excamera.com/sphinx/fpga-j1.html

Implemented in 200 lines of code.

These are some good references IMHO.
 

Differ, you may. But I observe that the first example was
indeed a team effort (after the initial concept evening) and
is still not done (github mentions a 2019 expected date)
while the second is indeed a uC level of complexity and
byte-sized (16 bits but aligned as byte pairs - ala 6809)
and the author says "we" (team, evidently).

There's nothing wrong with those works but they seem to
support my assertions well enough.

On the other, other hand the OP's goals are modest as
regards the ALU (2 operations?) and maybe the complexity
-is- on the order of a small uC.
 

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