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    [VERILOG] How to generate FIFO WRITE SIGNAL in COUNTER MODULE ?

    My normal counter code

    Code:
    module counter
    
    (
    	input clk, enable, rst_n,
    	output  reg[31:0] count
    );
    
    	always @ (posedge clk or negedge rst_n)
    	begin
    		if (~rst_n)
    			count <= 0;
    		else if (enable == 1'b1)
    			count <= count + 1;
    	end
    
    endmodule
    I am trying to implement the above code in Quartus and NIOS.

    counter's clock speed is 50MHz, So counter data is missing in NIOS console.

    So i need to give control to FIFO (write signal) through VERILOG.

    I need to change my counter design to check whether the fifo is full or not and only write the value (and increment the counter) when the fifo is not full. Please suggest me ,

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    Re: [VERILOG] How to generate FIFO WRITE SIGNAL in COUNTER MODULE ?

    How to generate FIFO WRITE SIGNAL in COUNTER MODULE ?
    Depends on the design.
    The write signal can be always '1', toggling with the clock, toggling at specific intervals, etc. This depends heavily on the nature of the write side of the FIFO.

    I need to change my counter design to check whether the fifo is full or not and only write the value (and increment the counter) when the fifo is not full.
    If you are using the FIFO IP, then the FIFO full flag is already there to be used.
    .....yes, I do this for fun!



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  3. #3
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    Re: [VERILOG] How to generate FIFO WRITE SIGNAL in COUNTER MODULE ?

    Thanks for your response. I am working with ALTERA quartus software tool.

    Simple Counter with FIFO is working. Working Design flow as mentioned (screenshot) as below
    Code:
    module counter
    (
    	input clk, enable, rst_n,
    	output  reg[31:0] count
    );
    	always @ (posedge clk or negedge rst_n)
    	begin
    		if (~rst_n)
    			count <= 0;
    		else if (enable == 1'b1)
    			count <= count + 1;
    	end
    endmodule
    The above design is working (generated only counter data). In the following design, i have done some modification, in verilog code i am generating Trigger and counter data.
    Code:
    module Counter(
        input clk,
    	 input enable,
        input reset,
        output reg[31:0] Final_value,
        output reg trig
        );
        reg[31:0] counter_out;
        reg [7:0] temp;
        reg [31:0] counter_result;
        wire temp1;
        wire temp2; 
           
        always@(posedge clk or negedge reset)
        begin
        if(~reset)
            begin
            trig<=0;
            temp<=0;
            counter_out<=0;
            end
        else if(enable==1'b1)
            begin
            counter_out<=counter_out+1;
            temp<=temp+1;
            if(temp==25)
                begin
                temp<=0;
                trig<=~trig;
                end
            end
            end 
    	 assign temp1=trig;
    	 assign temp2=temp1&&clk;
    	 always@(posedge temp2 or negedge reset)
    	 if(~reset)
    	    counter_result<=0;   
    	  else 
    	 begin
            counter_result<=counter_result+1;
         end
      always@(posedge trig or negedge reset)
      if(~reset)
           Final_value<=0;  
       else 
      begin
           Final_value<=counter_result;
      end
    endmodule
    Can anyone check my design. Whether i doing right or wrong.



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