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    Innovus (SoC Encounter) Post Layout Power Estimation

    Hi All,

    Is there a way to estimate Post Layout Power consumption (against switching activities) along with parasitics in Innovus instead of doing spice simulation on the streamed out GDS in virtuoso ?

    Thanks

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    Re: Innovus (SoC Encounter) Post Layout Power Estimation

    Quote Originally Posted by ranaya View Post
    Hi All,

    Is there a way to estimate Post Layout Power consumption (against switching activities) along with parasitics in Innovus instead of doing spice simulation on the streamed out GDS in virtuoso ?

    Thanks
    post-layout? I assume you are talking about analog. If so, the answer is no, you cannot (easily) load an analog circuit into innovus and get power from it.
    If you are talking about digital design, then the command is report_power.
    Really, I am not Sam.



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    Re: Innovus (SoC Encounter) Post Layout Power Estimation

    Hi, no I was referring to a digital design after the P&R is performed. This is with parasitics of the layout, so that power estimate will be more accurate. Can report_power generate the power numbers based on switching activity ?



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    Re: Innovus (SoC Encounter) Post Layout Power Estimation

    Quote Originally Posted by ranaya View Post
    Hi, no I was referring to a digital design after the P&R is performed. This is with parasitics of the layout, so that power estimate will be more accurate. Can report_power generate the power numbers based on switching activity ?
    Of course it can, that is all it does. The power reports get incrementally more detailed as you go through the implementation steps.
    Really, I am not Sam.



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    Re: Innovus (SoC Encounter) Post Layout Power Estimation

    Hi, now I want to compare the power consumption between the synthesized design (design compiler) and the post layout design (Innovus) based on a switching activity file. The first one can be easily done by generating an .saif file from post synthesis simulation (requires synthesized netlist and .sdf file).

    1. For the post layout activity file, I suppose I have to do the same simulation with post layout netlist and .sdf file (these are the only two ?) and this .sdf should have extracted parasitic delays ?

    2. Innovus does not seem to accept .saif for report_power (does for VCD). If I use the .vcd for that, would the power comparison be 1 to 1 ?

    Thanks



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  6. #6
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    Re: Innovus (SoC Encounter) Post Layout Power Estimation

    Quote Originally Posted by ranaya View Post
    Hi, now I want to compare the power consumption between the synthesized design (design compiler) and the post layout design (Innovus) based on a switching activity file. The first one can be easily done by generating an .saif file from post synthesis simulation (requires synthesized netlist and .sdf file).

    1. For the post layout activity file, I suppose I have to do the same simulation with post layout netlist and .sdf file (these are the only two ?) and this .sdf should have extracted parasitic delays ?

    2. Innovus does not seem to accept .saif for report_power (does for VCD). If I use the .vcd for that, would the power comparison be 1 to 1 ?

    Thanks
    VCD is the preferred file format for Innovus.
    All you need is a new VCD obtained from simulating the finished layout. The SDF file will capture the effect of parasitics.
    Really, I am not Sam.



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