Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Pipeline valid and ready signals semantic meaning

Status
Not open for further replies.

promach

Advanced Member level 4
Joined
Feb 22, 2016
Messages
1,199
Helped
2
Reputation
4
Reaction score
5
Trophy points
1,318
Activity points
11,636
wReady[0] = ~rValid[1] | wReady[1]
wReady[0] = ~$past(_rValid[1]) | wReady[1]
wReady[0] = ~$past(rValid[0] | (rValid[1] & ~wReady[1])) | wReady[1]
wReady[0] = $past(~rValid[0] & (~rValid[1] | wReady[1])) | wReady[1]
WR_DATA_READY = $past(~WR_DATA_VALID & (~RD_DATA_VALID | RD_DATA_READY)) | RD_DATA_READY

For pipeline, do you guys have any comments about the above expression for WR_DATA_READY which is derived from line 40 and 59 of the following verilog code or reg_pipeline.v ?


Code Verilog - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
module reg_pipeline
    #(
      parameter C_DEPTH = 1,
      parameter C_WIDTH = 128
      )
    (
     input                CLK,
     input                RST_IN,
 
     input [C_WIDTH-1:0]  WR_DATA,
     input                WR_DATA_VALID,
     output               WR_DATA_READY,
 
     output [C_WIDTH-1:0] RD_DATA,
     output               RD_DATA_VALID,
     input                RD_DATA_READY
     );
 
    genvar                i;
 
    wire                  wReady [C_DEPTH:0];
    
    reg [C_WIDTH-1:0]     _rData [C_DEPTH:1], rData [C_DEPTH:0];
    reg                   _rValid [C_DEPTH:1], rValid [C_DEPTH:0];
 
    // Read interface
    assign wReady[C_DEPTH] = RD_DATA_READY;
    assign RD_DATA = rData[C_DEPTH];
    assign RD_DATA_VALID = rValid[C_DEPTH];
 
    // Write interface
    assign WR_DATA_READY = wReady[0];
    always @(*) begin
        rData[0] = WR_DATA;
        rValid[0] = WR_DATA_VALID;
    end
 
    generate
        for( i = 1 ; i <= C_DEPTH; i = i + 1 ) begin : gen_stages
            assign #1 wReady[i-1] =  ~rValid[i] | wReady[i];
 
            // Data Registers
            always @(*) begin
                _rData[i] = rData[i-1];
            end
 
            // Enable the data register when the corresponding stage is ready
            always @(posedge CLK) begin
                if(wReady[i-1]) begin
                    rData[i] <= #1 _rData[i];
                end
            end
 
            // Valid Registers
            always @(*) begin
                if(RST_IN) begin
                    _rValid[i] = 1'b0;
                end else begin
                    _rValid[i] = rValid[i-1] | (rValid[i] & ~wReady[i]);
                end
            end
 
            // Always enable the valid registers
            always @(posedge CLK) begin
                rValid[i] <= #1 _rValid[i];
            end
 
        end
    endgenerate
endmodule

 
Last edited:

In what context? I assume simulation or verification as $past is not synthesisable.
 

input [C_WIDTH-1:0] WR_DATA, // Write data input
input WR_VALID, // Write enable, high active
output WR_READY, // ~Full condition

output [C_WIDTH-1:0] RD_DATA, // Read data output
input RD_READY, // Read enable, high active
output RD_VALID // ~Empty condition


I have understood it. Try to have a look at fifo.v or above input / output declaration and their code comments




Code Verilog - [expand]
1
WR_DATA_READY = $past(~WR_DATA_VALID & (~RD_DATA_VALID | RD_DATA_READY)) | RD_DATA_READY




is similar to



Code Verilog - [expand]
1
WR_READY = $past(~WR_VALID & (~RD_VALID | RD_READY)) | RD_READY

 

But I don't understand what question you are asking?
What are you trying to achieve
 

My comment is your expression makes no sense without more context. $past is mostly used in assertions.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top