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  1. #1
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    Pipeline valid and ready signals semantic meaning

    wReady[0] = ~rValid[1] | wReady[1]
    wReady[0] = ~$past(_rValid[1]) | wReady[1]
    wReady[0] = ~$past(rValid[0] | (rValid[1] & ~wReady[1])) | wReady[1]
    wReady[0] = $past(~rValid[0] & (~rValid[1] | wReady[1])) | wReady[1]
    WR_DATA_READY = $past(~WR_DATA_VALID & (~RD_DATA_VALID | RD_DATA_READY)) | RD_DATA_READY
    For pipeline, do you guys have any comments about the above expression for WR_DATA_READY which is derived from line 40 and 59 of the following verilog code or reg_pipeline.v ?

    Code Verilog - [expand]
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    module reg_pipeline
        #(
          parameter C_DEPTH = 1,
          parameter C_WIDTH = 128
          )
        (
         input                CLK,
         input                RST_IN,
     
         input [C_WIDTH-1:0]  WR_DATA,
         input                WR_DATA_VALID,
         output               WR_DATA_READY,
     
         output [C_WIDTH-1:0] RD_DATA,
         output               RD_DATA_VALID,
         input                RD_DATA_READY
         );
     
        genvar                i;
     
        wire                  wReady [C_DEPTH:0];
        
        reg [C_WIDTH-1:0]     _rData [C_DEPTH:1], rData [C_DEPTH:0];
        reg                   _rValid [C_DEPTH:1], rValid [C_DEPTH:0];
     
        // Read interface
        assign wReady[C_DEPTH] = RD_DATA_READY;
        assign RD_DATA = rData[C_DEPTH];
        assign RD_DATA_VALID = rValid[C_DEPTH];
     
        // Write interface
        assign WR_DATA_READY = wReady[0];
        always @(*) begin
            rData[0] = WR_DATA;
            rValid[0] = WR_DATA_VALID;
        end
     
        generate
            for( i = 1 ; i <= C_DEPTH; i = i + 1 ) begin : gen_stages
                assign #1 wReady[i-1] =  ~rValid[i] | wReady[i];
     
                // Data Registers
                always @(*) begin
                    _rData[i] = rData[i-1];
                end
     
                // Enable the data register when the corresponding stage is ready
                always @(posedge CLK) begin
                    if(wReady[i-1]) begin
                        rData[i] <= #1 _rData[i];
                    end
                end
     
                // Valid Registers
                always @(*) begin
                    if(RST_IN) begin
                        _rValid[i] = 1'b0;
                    end else begin
                        _rValid[i] = rValid[i-1] | (rValid[i] & ~wReady[i]);
                    end
                end
     
                // Always enable the valid registers
                always @(posedge CLK) begin
                    rValid[i] <= #1 _rValid[i];
                end
     
            end
        endgenerate
    endmodule
    Last edited by promach; 13th September 2018 at 09:25.

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  2. #2
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    Re: Pipeline valid and ready signals semantic meaning

    In what context? I assume simulation or verification as $past is not synthesisable.



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  3. #3
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    Re: Pipeline valid and ready signals semantic meaning

    input [C_WIDTH-1:0] WR_DATA, // Write data input
    input WR_VALID, // Write enable, high active
    output WR_READY, // ~Full condition

    output [C_WIDTH-1:0] RD_DATA, // Read data output
    input RD_READY, // Read enable, high active
    output RD_VALID // ~Empty condition

    I have understood it. Try to have a look at fifo.v or above input / output declaration and their code comments



    Code Verilog - [expand]
    1
    
    WR_DATA_READY = $past(~WR_DATA_VALID & (~RD_DATA_VALID | RD_DATA_READY)) | RD_DATA_READY


    is similar to


    Code Verilog - [expand]
    1
    
    WR_READY = $past(~WR_VALID & (~RD_VALID | RD_READY)) | RD_READY



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  4. #4
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    Re: Pipeline valid and ready signals semantic meaning

    But I don't understand what question you are asking?
    What are you trying to achieve



  5. #5
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    Re: Pipeline valid and ready signals semantic meaning

    My comment is your expression makes no sense without more context. $past is mostly used in assertions.
    Dave Rich
    Senior Verification Consultant
    Mentor Graphics Corporation



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